Verification Engineer

TPI Global Solutions; Austin (TX); On-site; USD 140,000 - 190,000; Full time

Job summary

TPI Global Solutions in Austin, TX seeks a senior verification engineer specializing in formal verification. You will lead development and execution of formal verification strategies using SVA, FPV, and UVM-based methodologies to ensure functional correctness in complex designs.

The ideal candidate has 8–10 years of hands-on experience with VC Formal or Jasper Gold, strong scripting skills (TCL, Python, Perl), and a track record of automating verification flows and achieving robust coverage.

Qualifications

• Hands-on experience with VC Formal (Synopsys) and/or Jasper Gold (Cadence).
• Strong proficiency in System Verilog Assertions (SVA) and formal property specification.
• Experience with FPV, connectivity checking, register verification, equivalence checking, and coverage analysis.
• Familiarity with scripting languages (TCL, Python, Perl) for flow automation.
• Extensive experience in design verification with a strong focus on formal verification.
• Expertise in System Verilog and UVM-based verification methodologies.
• A minimum of 8–10 years of experience is required.

Skills

SVA & properties

VC Formal / Jasper Gold

FPV & coverage analysis

SystemVerilog & UVM

8–10 years experience

Tools

VC Formal

Jasper Gold

Job description

• Hands-on experience with VC Formal (Synopsys) and/or Jasper Gold (Cadence).
• Strong proficiency in System Verilog Assertions (SVA) and formal property specification.
• Experience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysis.
• Familiarity with scripting languages (TCL, Python, Perl) for flow automation.
• Extensive experience in design verification with a strong focus on formal verification.
• Expertise in System Verilog and UVM-based verification methodologies.
• A minimum of 8–10 years of experience is required.