Senior ASIC/SoC Validation Engineer

TechDoQuest; San Jose (CA); Presencial; USD 150.000 - 190.000; Jornada completa

Descripción de la vacante

TechDoQuest in California is seeking an experienced ASIC verification engineer to verify complex blocks of SoCs as part of a joint CPU/GPU development effort. You will design and execute test plans using directed and constrained-random tests, and document verification procedures to ensure functional correctness.

The role requires 8–10 years of proven verification experience on large ASIC projects or equivalent software/firmware experience in hardware development, with a strong background in

Formación

• 8–10 years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting.
• Strong background in C/C++ development in a Linux Environment.
• Proficient in Object Oriented programming, STL, computer architecture and data structures.
• Experience in Verilog/SystemVerilog/SystemC, preferred; DPI/PLI experience preferred.
• Strong debugging skills and experience with debug tools such as Gdb, Valgrind.
• Excellent written and communication skills; Prefer SoC verification experience and UVM (System Verilog).

Responsabilidades

• Participate in the functional verification of ASIC blocks and IP cores.
• Documentation and execution of test plan(s) with directed and constrained-random tests during simulation.
• Adopt evolving verification methodologies for complex SoCs within aggressive schedules.
• Work within the existing verification infrastructure on active projects and collaborate with design/verification teams.

Conocimientos

C/C++ development

Debugging skills

Object oriented programming

Computer architecture

Data structures

Communication skills

Analytical skills

Herramientas

GDB

Valgrind

Perl

Makefiles

Verilog/SystemVerilog/SystemC

DPI/PLI

Descripción del empleo

TechDoQuest in California is seeking an experienced ASIC verification engineer to verify complex blocks of SoCs as part of a joint CPU/GPU development effort. You will design and execute test plans using directed and constrained-random tests, and document verification procedures to ensure functional correctness.

The role requires 8–10 years of proven verification experience on large ASIC projects or equivalent software/firmware experience in hardware development, with a strong background in