TPU Design Engineer, Silicon

Google; United States; On-site; USD 138,000 - 197,000; Full time

Job summary

Google is hiring a TPU Design Engineer, Silicon in Mountain View, CA or San Diego, CA. You will work on custom silicon for Google's hardware products, with a focus on RTL design, power-aware implementations, and high-performance blocks.

This role requires strong digital design skills and collaborative leadership within multi-disciplinary teams. Minimum qualifications include a Bachelor's degree or equivalent, 4 years in RTL/Verilog/SystemVerilog, and experience with logic synthesis for power and

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 4 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
• Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.

Responsibilities

• Use simulation/emulation/power analysis tools to ensure power and performance meet defined specifications.
• Develop, implement, and maintain design blocks or components/parts of a hardware product, and integrate them into subsystems.
• Engage with Verification and Silicon Validation teams to ensure functionality of the design.
• Provide input on synthesis, timing closure, and Physical Design of digital blocks.
• Take a leadership role on technical project teams and set technical direction.

Skills

Digital logic design

RTL design

Verilog

SystemVerilog

Logic synthesis

Low-power design

Education

Bachelor's degree or equivalent experience

Master's or PhD (preferred)

Job description

TPU Design Engineer, Silicon

Google; Mountain View, CA, USA; San Diego, CA, USA

Mid

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Mountain View, CA, USA; San Diego, CA, USA.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
• 4 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
• Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Knowledge of accelerators (e.g., Machine Learning or GPUs) or similar high performance designs.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Use simulation/emulation/power analysis tools and techniques to ensure power and performance meet defined specifications.
• Develop, implement, and maintain design blocks or components/part of a hardware product, and integrate design blocks or components/parts to create product subsystems.
• Engage with Verification and Silicon Validation teams to ensure functionality of the design
• Provide input on synthesis, timing closure, and Physical Design of digital blocks
• Take a leadership role on technical project teams and set technical direction.

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