Senior Design and Integration Engineer, Cloud TPU

Google Inc.; Sunnyvale (CA); On-site; USD 163,000 - 237,000; Full time

Benefits offered by this job

15% bonus target

Equity

Comprehensive benefits package

Job summary

Google Inc. in Sunnyvale, CA is seeking a Senior Design and Integration Engineer for Cloud TPU. In this role, you will shape the future of AI/ML hardware by driving the design and optimization of Tensor Processing Units (TPUs). Responsibilities include defining microarchitecture, collaborating with various teams, and leading power optimization initiatives.

The ideal candidate should have a Bachelor's degree in a related field and 8 years of RTL design experience. Compensation ranges from $163,000 to $237,000 annually, accompanied by a bonus and equity.

Qualifications

• 8 years of experience in RTL design.
• Cross-functional experience with DV and PD teams.
• Experience optimizing for performance, power, and area.

Responsibilities

• Define and document the microarchitecture for digital designs within the TPU.
• Drive critical power optimization and automation initiatives.
• Support post-silicon validation and hardware debugging.

Skills

RTL design

Digital design

Microarchitecture design

Power optimization

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

PowerArtist

PTPX

Python

Perl

Job description

Senior Design and Integration Engineer, Cloud TPU

Sunnyvale, CA, USA. Level: Mid.

Job Summary

Shape the future of AI/ML hardware acceleration by driving the design, optimization, and integration of next‑generation Tensor Processing Units (TPUs). Work closely with Verification, Physical Design, Validation, and Firmware teams to deliver cutting‑edge hardware for Google’s AI workloads.

Responsibilities

• Define and document the microarchitecture for digital designs within the TPU.
• Partner with Verification to develop test plans and debug RTL, and collaborate with Physical Design to meet timing, area, power, and manufacturability goals.
• Drive critical power optimization and automation initiatives across all on‑chip‑network components and subsystems.
• Support post‑silicon validation and hardware debugging to ensure successful deployment.
• Lead the development and enhancement of internal design tools, flows, and engineering methodologies.

Required Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 8 years of experience in RTL design.
• Experience with digital and microarchitecture design.
• Cross‑functional experience with DV and PD teams.
• Experience optimizing for performance, power, and area.

Preferred Qualifications

• Master’s degree or PhD with emphasis on computer architecture.
• 10 years of RTL design experience.
• 4 years of experience in power optimization and use of tools such as PowerArtist and PTPX.
• Experience with linting, CDC, RDC, LEC, and scripting languages (Python or Perl).
• Experience optimizing RTL solutions, design methodologies, and automating front‑end engineering flows.
• Experience in design automation, RTL architecture, and ASIC synthesis flows.

Compensation

US: $163,000 - $237,000 (USD) + 15% bonus target + equity + benefits.

Benefits

Learn more about benefits at Google.

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Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.