TPU SoC Design Engineer, Google Cloud

Google; Sunnyvale (CA); On-site; USD 116,000 - 166,000; Full time

Job summary

Google is seeking an Early TPU SoC Design Engineer in Sunnyvale, CA to help shape AI/ML hardware acceleration and contribute to TPU architecture, RTL design, and verification. You will work on SoC-level RTL design, high-level integration, and cross‑functional collaboration across engineering teams.

The role offers exposure to cutting-edge ASIC development and advancement opportunities in a fast‑moving environment.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience.
• 2 years of experience in ASIC RTL design using SystemVerilog or Verilog.
• Experience with industry-standard EDA tools for simulation, synthesis, and power analysis.
• Experience with digital design, including synchronous and asynchronous logic, state machines, and bus protocols.

Responsibilities

• Define and document the microarchitecture for digital designs within the TPU.
• Write performant, and power‑efficient RTL code, primarily in SystemVerilog.
• Collaborate with the Verification team to develop test plans, debug RTL, and ensure functional correctness.
• Work with the Physical Design team to meet timing, area, power, and manufacturability requirements.
• Contribute to the development and enhancement of design tools, flows, and methodologies.

Skills

ASIC RTL design

SystemVerilog/Verilog

Digital design concepts

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience.

Tools

EDA tools for simulation, synthesis, power analysis

Job description

TPU SoC Design Engineer, Google Cloud

Location: Sunnyvale, CA, USA

Early

Experience completing work as directed, and collaborating with teammates; developing knowledge of relevant concepts and processes.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience.
• 2 years of experience in ASIC RTL design using systemverilog or verilog.
• Experience with industry-standard EDA tools for simulation, synthesis, and power analysis.
• Experiecnce with digital design, including synchronous and asynchronous logic, state machines, and bus protocols.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering or Computer Engineering, with an emphasis on computer architecture.
• 5 years of experience with RTL coding using Verilog/SystemVerilog.
• Experience in scripting (e.g., Python, Tcl, or Perl) and debugging with tools like Verdi or VCS.
• Experience with SOC implementation standards and interfaces (e.g., AXI).
• Experience architecting RTL solutions employing software based construction, instantiation, customization and generation of RTL.
• Experience with CDC, UPF, RDC, RTL Linting, and LEC.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google’s most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google’s TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will be working on SoC-level RTL design for our data center accelerators. You will work on top-level RTL, architecture, design and implementation of global communication busses, and integration of complex ASIC designs. This is a cross‑functional and central role that will require interactions with numerous ASIC development teams. You will own deliverables to the cross‑functional teams (e.g., Physical Design, Verification, Validation, Firmware) at various project milestones. You will also be directly involved in defining and creating methodologies that enable an efficient design environment for all ASIC engineers.

You will be a key contributor to the development of Google’s AI accelerators. You will create innovative and efficient hardware solutions. You will have the opportunity to work on technical problems at the forefront of AI hardware, working in a dynamic and collaborative environment.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We’re the driving force behind Google’s groundbreaking innovations, empowering the development of our cutting‑edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world‑leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job‑related skills, experience, and relevant education or training.

US: $116000 - $166000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Define and document the microarchitecture for digital designs within the TPU.
• Write performant, and power‑efficient Register Transfer Level (RTL) code, primarily in SystemVerilog.
• Collaborate with the Verification team to develop test plans, debug RTL, and ensure functional correctness.
• Work with the Physical Design team to meet timing, area, power, and manufacturability requirements.
• Contribute to the development and enhancement of design tools, flows, and methodologies.

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