TPU Compute RTL Design Engineer

Anysilicon; Sunnyvale (CA); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Google in Sunnyvale, CA is seeking an experienced ASIC Design Engineer to develop custom silicon for data-center products, focusing on efficiency and integration. You will define microarchitecture, write SystemVerilog RTL, and collaborate across software, architecture, and physical design teams.

The role emphasizes power, performance, and area optimizations, validation planning, and timing closure to meet aggressive hardware requirements.

Qualifications

• 8 years of experience in digital design using SystemVerilog RTL.
• Experience with power, performance, and area optimizations.
• Experience collaborating with software, architecture, and physical design teams.

Responsibilities

• Create and review microarchitecture specifications for the compute subsystem design.
• Define integration requirements for the compute subsystem to the System on Chip (SoC).
• Develop SystemVerilog RTL to implement logic for ASIC products, adhering to coding and quality guidelines.
• Collaborate with design validation teams to create test plans for verifying and debugging design RTL.
• Work with physical design teams to ensure designs meet physical requirements and achieve timing closure.

Skills

Collaboration with software/arch/PD

Knowledge of processors/accelerators/m

Education

Bachelor's degree in EE/CE/CS or related

Tools

SystemVerilog RTL

Job description

Join Google's innovative team as an ASIC Design Engineer, where you'll develop custom silicon solutions that enhance the performance of direct-to-consumer products. Your work will contribute to the next generation of hardware experiences, focusing on efficiency and integration in data center accelerators.

Responsibilities:

• Create and review microarchitecture specifications for the compute subsystem design.
• Define integration requirements for the compute subsystem to the System on Chip (SoC).
• Develop SystemVerilog RTL to implement logic for ASIC products, adhering to coding and quality guidelines.
• Collaborate with design validation teams to create test plans for verifying and debugging design RTL.
• Work with physical design teams to ensure designs meet physical requirements and achieve timing closure.

Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in digital design using SystemVerilog RTL.
• Experience with power, performance, and area optimizations.

Skills:

• Experience collaborating with software, architecture, and physical design teams.
• Knowledge of processor design, accelerators, or memory hierarchies.