TPU ASIC Verification Manager

Google Inc.; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google is seeking an ASIC Design Verification Manager to lead the TPU verification team and own functional verification across subchip, subsystem, and full-chip levels. You will develop test plans, build monitors, and drive architectural compliance for AI/ML hardware acceleration.

Join a world-class team shaping TPU architecture and contributing to Google's most demanding AI/ML applications, collaborating with front-end design, architecture, and performance teams to meet performance goals.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 10 years of experience with verification, SystemVerilog, and UVM.
• 3 years of experience in people management.

Responsibilities

• Lead ASIC design verification for TPU, guiding the development of advanced verification infrastructure across subchip, subsystem, and full-chip levels.
• Develop comprehensive test plans, write diagnostic codes, and build monitors and checkers to ensure quality assurance.
• Partner closely with front-end design, architecture, and performance teams to ensure architectural compliance and meet performance goals.
• Analyze coverage across multiple dimensions to drive verification quality and meet key performance targets.

Skills

verification

SystemVerilog

UVM

people management

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

UVM

SystemVerilog

Job description

Google is seeking an ASIC Design Verification Manager to lead the TPU verification team and own functional verification across subchip, subsystem, and full-chip levels. You will develop test plans, build monitors, and drive architectural compliance for AI/ML hardware acceleration.

Join a world-class team shaping TPU architecture and contributing to Google's most demanding AI/ML applications, collaborating with front-end design, architecture, and performance teams to meet performance goals.