Senior ASIC Verification Lead for AI Accelerators

Google; Sunnyvale (CA); Hybrid; USD 240,000 - 333,000; Full time

Job summary

Google is seeking an ASIC Design Verification Technical Lead to shape verification strategies for TPU architecture and AI accelerators. You will drive emulation and post-silicon correlation, define verification architectures, and ensure RTL meets our architectural goals in high-speed DSP pipelines.

You will lead co-simulation, coverage, and method improvements across pre- and post-silicon stages, collaborating with DSP and algorithm teams to deliver robust digital designs for Google's data

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 12 years of experience in design verification.
• Experience in high-speed PHY layers, high-speed interface subsystems, or mixed-signal verification.

Responsibilities

• Design, build, and scale constrained-random verification environments using SystemVerilog and UVM for high-speed physical-layer DSP blocks.
• Build co-simulation frameworks and predictors to compare RTL implementation output against high-level algorithmic models.
• Define and execute functional coverage plans, utilizing covergroups and SystemVerilog Assertions to verify architectural corner cases, fixed-point quantization effects, and numerical overflows.
• Author dynamic stimulus sequences and virtual sequencers to stress-test adaptive feedback loops under realistic channel impairments, including noise, ISI, and high-frequency jitter profiles.
• Lead the debugging of RTL and environment failures, collaborating closely with algorithm and DSP designers to isolate and resolve discrepancies between the RTL implementation and the specification.

Skills

Design verification

High-speed PHY

High-speed interfaces

Mixed-signal verification

Education

Bachelor's degree in Electrical/Computer Engineering

Master's or PhD in Electrical/Computer Engineering

Tools

SystemVerilog

UVM

Job description

Google is seeking an ASIC Design Verification Technical Lead to shape verification strategies for TPU architecture and AI accelerators. You will drive emulation and post-silicon correlation, define verification architectures, and ensure RTL meets our architectural goals in high-speed DSP pipelines.

You will lead co-simulation, coverage, and method improvements across pre- and post-silicon stages, collaborating with DSP and algorithm teams to deliver robust digital designs for Google's data