ASIC Verification Engineer for TPU AI Accelerators

Google Inc.; Sunnyvale (CA); On-site; USD 138,000 - 198,000; Full time

Benefits offered by this job

15% bonus target

Equity

Comprehensive benefits

Job summary

Google Inc. in Sunnyvale, CA, is looking for an ASIC Design Verification Engineer to shape the future of AI/ML hardware acceleration. In this role, you will drive cutting-edge TPU technology and be part of a team developing custom silicon solutions.

You will have responsibilities including planning verification, creating verification environments, and debugging designs. Candidates must possess a Bachelor's degree in Electrical Engineering or a related field and have at least 4 years of design verification experience.

Qualifications

• 4 years of experience with design verification.
• Experience with SystemVerilog/Verilog.
• Familiarity with ASIC standard interfaces.

Responsibilities

• Plan the verification of complex digital design blocks.
• Create a constrained‑random verification environment using SystemVerilog.
• Debug tests with design engineers.

Skills

Design verification

SystemVerilog

UVM

ASIC architecture

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree or PhD in relevant field (preferred)

Tools

Industry standard tools

Job description

Google Inc. in Sunnyvale, CA, is looking for an ASIC Design Verification Engineer to shape the future of AI/ML hardware acceleration. In this role, you will drive cutting-edge TPU technology and be part of a team developing custom silicon solutions.

You will have responsibilities including planning verification, creating verification environments, and debugging designs. Candidates must possess a Bachelor's degree in Electrical Engineering or a related field and have at least 4 years of design verification experience.