Lead ATE Test Engineer for SoC & High-Speed

Astera Labs; San Jose (CA); On-site; USD 150,000 - 210,000; Full time

Benefits offered by this job

Flexible time off in the US

Parental leave

401K

Retirement and pension plans

Medical, dental, and vision plans

Job summary

Astera Labs is seeking a Principal ATE Test Engineer to lead the development and support of complex mixed-signal silicon SoC test solutions. You will drive ATE programs from design to high-volume production and collaborate with manufacturing partners to optimize tester resources and coverage.

The candidate should have strong knowledge of high-speed protocols (PCIe, Ethernet, Infiniband, DDR, NVMe, USB) and a solid EE foundation with 8+ years of release experience.

Qualifications

• Bachelor’s in Electrical Engineering required; Master’s preferred.
• 8+ years experience releasing complex SoC to high-volume manufacturing.
• Experience with ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug.
• Proficiency in C/C++ and Python; strong communication and teamwork.

Responsibilities

• Develop and oversee SoC test strategy for high-volume manufacturing.
• Interact with manufacturing partners to define and implement ATE programs.
• Own the product from design, initial samples through ramp to high volume production.
• Collaborate with design team to define test strategy and test plans.
• Lead test pattern optimization and DFx for maximum coverage and yield.

Skills

ATE programming

C/C++

Python

SerDes 16Gbps+

Test pattern optimization

DFT techniques

SCAN

MEMBIST

Oscilloscopes

Protocol analyzers

Education

Bachelor’s in Electrical Engineering

Master’s degree preferred

Tools

Teradyne ATE

Advantest 93k ATE

Load boards design

Oscilloscopes

Protocol analyzers

Job description

Astera Labs is seeking a Principal ATE Test Engineer to lead the development and support of complex mixed-signal silicon SoC test solutions. You will drive ATE programs from design to high-volume production and collaborate with manufacturing partners to optimize tester resources and coverage.

The candidate should have strong knowledge of high-speed protocols (PCIe, Ethernet, Infiniband, DDR, NVMe, USB) and a solid EE foundation with 8+ years of release experience.