ASIC Digital Design, Sr Staff Engineer

Anysilicon; Boxborough (MA); On-site; USD 120,000 - 180,000; Full time

Job summary

Synopsys is seeking an experienced ASIC digital designer or verifier to join our team in Massachusetts. You will contribute to high-performance silicon chips and software content, and participate in RTL and gate-level simulations, supporting customers on HBM/DDR PHY topics.

Responsibilities include creating test benches, debugging, and developing technical documentation, while driving product improvements based on customer feedback and data from engineering teams.

Qualifications

• Specialization in ASIC RTL design and verification.
• Experience with Verilog, PERL, TCL, and Python.
• Knowledge of static timing analysis and synthesis.
• Simulation and debugging abilities.
• Experience with HBM/DDR protocol is a plus.

Responsibilities

• Create and debug test benches and test cases.
• Run RTL and gate-level simulations.
• Support application engineers and customers on HBM/DDR PHY topics.
• Contribute to technical documentation.
• Drive product improvements based on customer feedback.

Skills

Analytical thinking

Strong communication

Adaptability

Tools

Verilog

PERL

TCL

Python

Static timing analysis

Synthesis

Job description

Synopsys is at the forefront of technological innovation, driving advancements in chip design, verification, and IP integration. We are seeking an experienced ASIC digital designer or verifier to join our team and contribute to the development of high-performance silicon chips and software content. This role is available in multiple locations, including Markham, Mississauga, Ottawa–Nepean, and Boxborough, Massachusetts.

Responsibilities:

• Create and debug test benches and test cases.
• Run RTL and gate-level simulations.
• Support application engineers and customers on HBM/DDR PHY topics.
• Contribute to technical documentation.
• Drive product improvements based on customer feedback.

Qualifications:

• Specialization in ASIC RTL design and verification.
• Experience with Verilog, PERL, TCL, and Python.
• Knowledge of static timing analysis and synthesis.
• Simulation and debugging abilities.
• Experience with HBM/DDR protocol is a plus.

Skills:

• Analytical thinking and problem-solving skills.
• Strong communication and collaboration abilities.
• Adaptability and customer-focused mindset.

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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