Technical Staff Engineer - Design Implementation

Microchip Technology Inc.; Chandler (AZ); On-site; USD 130,000 - 170,000; Full time

Job summary

Microchip Technology Inc. is looking for a senior silicon implementation engineer in Chandler, Arizona. This role involves developing advanced SoC implementation flows and mentoring engineers on best practices in design implementation.

The ideal candidate will have over 14 years of experience in SoC implementation, strong skills in timing closure, and a clear understanding of low-power digital design methodologies.

Qualifications

• 14+ years of experience in SoC implementation activities.
• Strong hands-on expertise in UPF specification and timing closure.
• Ability to develop effective timing constraints for complex SoCs.

Responsibilities

• Develop advanced SoC implementation flows for complex chips.
• Define timing methodologies for predictable signoff targets.
• Mentor engineers on design implementation flows and strategies.

Skills

Synthesis

Timing closure

Low-power digital design

Hierarchical implementation

Cross-functional communication

Education

BS or MS in Electrical Engineering

Tools

Genus

Tempus

Primetime

Design Compiler

Conformal

Job description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi‑billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally‑recognised Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values‑based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Job Description

We are seeking a senior silicon implementation engineer with deep expertise in methodology development and implementation flows for next generation 12 nm silicon, with particular focus on hierarchical SoC execution, timing convergence, and multi‑die design enablement. The successful candidate will play a central role in shaping scalable RTL‑to‑silicon methodologies and driving robust implementation practices across complex SoC programs.

Key Responsibilities

• Develop and deploy advanced SoC implementation flows for complex chips involving hierarchical design planning, logic synthesis, timing closure, power analysis, and low‑power implementation methodologies like UPF specification
• Define top‑level timing methodologies across IPs, subsystems, and full‑chip integration to ensure predictable convergence to signoff targets
• Drive design implementation methodology tailored for multi‑die integration, timing constraints strategy, and integration flows
• Influence design partitioning decisions by evaluating their impact on implementation complexity, timing closure, power, yield, and scalability
• Develop effective timing constraints for complex blocks and SoCs, including clock definition, exception strategy, interface budgeting
• Work well with physical design team to drive floorplanning decisions and clock tree constraints to meet key performance goals
• Mentor engineers on design implementation flows, timing closure strategies, and multi‑die design best practices

Requirements/Qualifications

• BS or MS in Electrical Engineering or related field with 14+ years of experience in SoC implementation activities
• Strong hands‑on expertise in synthesis, UPF specification, timing closure, hierarchical implementation, and low‑power digital design flows
• Hands‑on experience in industry standard EDA tools:
  • Genus/iSpatial/Design Compiler/Fusion Compiler
  • Tempus/Primetime
  • Prime Power/VCLP/RTL architect
  • Conformal/Formality
• Deep understanding of SoC timing architecture, including clocking strategy, constraint development, timing budgeting, and block‑to‑top convergence
• Ability to incorporate system‑level timing specifications into implementation constraints needed for synthesis and timing closure
• Good background in digital microarchitecture, RTL coding and front‑end to implementation handoff quality. Strong cross‑functional communication skills, and demonstrated technical leadership in ambiguous environments
• Demonstrated ability to build new process flows and scale implementation methodologies across teams. Proactively build new methodologies when existing flow do not scale
• Experience working in first‑generation product environments where flows, margins, and best practices must be established

Travel Time

0% – 25%

Physical Attributes

Hearing, Seeing, Talking

Physical Requirements

80% sitting , 10% standing, 10% walking

Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.

For more information on applicable equal employment regulations, please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.