Technical Staff Engineer - Design Implementation

FHLB Des Moines; Chandler (AZ); On-site; USD 130,000 - 160,000; Full time

Job summary

FHLB Des Moines is seeking a Senior Silicon Implementation Engineer with expertise in methodology development for 12nm silicon. The role involves developing advanced SoC implementation flows, defining timing methodologies, and mentoring engineers.

The ideal candidate will have at least 14 years of experience in SoC activities and a strong background in synthesis and timing closure. This position requires the ability to work with complex designs and communicate effectively across functions.

Qualifications

• 14+ years of experience in SoC implementation activities.
• Strong hands-on expertise in synthesis and timing closure.
• Deep understanding of SoC timing architecture and constraint development.

Responsibilities

• Develop and deploy advanced SoC implementation flows for complex chips.
• Define top-level timing methodologies across IPs and subsystems.
• Drive design implementation methodology tailored for multi-die integration.

Skills

Synthesis

Timing closure

Hierarchical implementation

Low-power digital design flows

Cross-functional communication

Technical leadership

Education

BS or MS in Electrical Engineering or related field

Job description

We are seeking a senior silicon implementation engineer with deep expertise in methodology development and implementation flows for next-generation 12nm silicon, with particular focus on hierarchical SoC execution, timing convergence, and multi-die design enablement.

Responsibilities

• Develop and deploy advanced SoC implementation flows for complex chips involving hierarchical design planning, logic synthesis, timing closure, power analysis, and low-power methodologies.
• Define top-level timing methodologies across IPs, subsystems, and full-chip integration to ensure predictable convergence to signoff targets.
• Drive design implementation methodology tailored for multi-die integration, including partition-aware RTL development, constraints strategy, and integration flows.
• Influence design partitioning decisions by evaluating their impact on implementation complexity, timing closure, power, yield, and scalability.
• Develop effective timing constraints for complex blocks and SoCs, including clock definition, exception strategy, interface budgeting.
• Mentor engineers on design implementation flows, timing closure strategies, and multi-die design best practices.

Qualifications

• BS or MS in Electrical Engineering or related field with 14+ years of experience in SoC implementation activities.
• Strong hands-on expertise in synthesis, timing closure, hierarchical implementation, and low-power digital design flows.
• Deep understanding of SoC timing architecture, including clocking strategy, constraint development, timing budgeting, and block-to-top convergence.
• Ability to incorporate system level timing specifications into implementation constraints needed for synthesis and timing closure.
• Good background in digital microarchitecture, and front-end to implementation handoff quality.
• Strong cross-functional communication skills, and demonstrated technical leadership in ambiguous environments.
• Demonstrated ability to build new process flows and scale implementation methodologies across teams.
• Proactively build new methodologies when existing flow do not scale.
• Experience working in first-generation product environments where flows, margins, and best practices must be established.

Travel

0% - 25%

Physical Attributes

Hearing, Seeing, Talking, Works Alone, Works Around Others.

Physical Requirements

90% Sitting, 10% Walking/Standing.

Equal Opportunity Statement

Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.