Tech Lead, SerDes/PHY IP Verification

Socket.dev; San Jose (CA); On-site; USD 160,000 - 200,000; Full time

Benefits offered by this job

Discretionary bonus

Benefits package

Job summary

Astera Labs in San Jose, CA seeks a Principal Design Verification Engineer to own the verification of high‑speed SerDes/PHY IP powering next‑gen AI infrastructure. You will architect UVM environments, drive coverage, and ensure first‑pass silicon success across analog/digital boundaries.

You will partner with PHY analog/mixed‑signal designers, digital architects, and SoC integration teams to verify multi‑Gbps SerDes blocks that interface PCIe Gen 6/7, UCIe, and Ethernet-based connectivity,

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 5+ years in design verification of high-speed SerDes or PHY.
• Strong SystemVerilog and UVM proficiency.
• Experience with AMS co-simulation and RNM modeling.
• Familiarity with PCIe/UCIe/UALink standards.

Responsibilities

• Architect UVM-based verification environments for SerDes/PHY IP.
• Define verification plans, coverage models, and sign-off criteria.
• Develop SystemVerilog/UVM testbenches and sequences.
• Lead coverage analysis and drive regressions to tape-out.
• Collaborate with analog/mixed-signal designers and SoC teams.

Skills

SystemVerilog

UVM

RNM

AMS co-simulation

SerDes/PHY IP

Python

PCIe/UCIe/UALink

Education

Bachelor's degree in Electrical Engineering

MS or PhD preferred

Tools

Palladium

Veloce

ZeBu

Job description

Astera Labs in San Jose, CA seeks a Principal Design Verification Engineer to own the verification of high‑speed SerDes/PHY IP powering next‑gen AI infrastructure. You will architect UVM environments, drive coverage, and ensure first‑pass silicon success across analog/digital boundaries.

You will partner with PHY analog/mixed‑signal designers, digital architects, and SoC integration teams to verify multi‑Gbps SerDes blocks that interface PCIe Gen 6/7, UCIe, and Ethernet-based connectivity,