Tech Lead: Power Integrity & IR/EM for SoCs

Astera Labs; San Jose (CA); On-site; USD 160,000 - 200,000; Full time

Job summary

Astera Labs is scaling the connectivity fabric behind the world’s largest AI clusters, and reliable power delivery is non-negotiable in the SoCs we ship. As a Technical Lead Physical Design Engineer- Power Integrity, you will own IR drop and EMIR analysis and closure across Astera Labs' connectivity ASIC portfolio, driving power integrity from early floorplan through tapeout.

You will partner closely with power grid, floorplan, package, and implementation teams to ensure stable power delivery,

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.

Responsibilities

• Own static and dynamic IR drop and electromigration analysis at block and full-chip levels to meet foundry sign-off criteria.
• Drive UPF-based power domain planning and power-aware sign-off across multi-voltage designs.
• Collaborate with package, power grid, and floorplan teams to identify and resolve voltage drop hotspots and EM violations early in the design cycle.

Skills

Power integrity

IR drop analysis

Electromigration (EMIR)

Scripting (Tcl/Python/Perl)

UPF-based planning

Flow automation

Sign-off criteria

Cadence Voltus

Synopsys RedHawk-SC / PrimeTime PX

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Tools

Cadence Voltus

Synopsys RedHawk-SC

PrimeTime PX

Job description

Astera Labs is scaling the connectivity fabric behind the world’s largest AI clusters, and reliable power delivery is non-negotiable in the SoCs we ship. As a Technical Lead Physical Design Engineer- Power Integrity, you will own IR drop and EMIR analysis and closure across Astera Labs' connectivity ASIC portfolio, driving power integrity from early floorplan through tapeout.

You will partner closely with power grid, floorplan, package, and implementation teams to ensure stable power delivery,