SystemC Modeling Developer

UST; Town of Poland (NY); On-site; USD 120,000 - 160,000; Full time

Job summary

UST seeks a highly skilled SystemC Modeling Developer to join the Server Architecture & Performance Engineering team. You will design and develop SystemC/TLM models for Compute and AI server platforms to drive architecture exploration and pre-silicon software development.

Responsibilities include building modular models, analyzing bottlenecks, and validating against RTL. You will work with virtual platforms and multiple simulators, collaborating with architects and performance teams to ensure

Qualifications

• Requires BS/MS in Computer Engineering, Electrical Engineering, Computer Science, or related field.
• 8+ years of experience in SystemC/TLM modeling, pre-silicon simulation, or architectural modeling for semiconductor/server platforms.

Responsibilities

• Develop SystemC/TLM2.0-based models for server subsystems (CPU, memory, I/O, accelerators, AI engines).
• Build modular, scalable models for Compute & AI workloads and integrate into simulation frameworks.
• Perform system-level performance modeling, profiling, and bottleneck analysis across compute, memory, and accelerator paths.
• Support pre-silicon BIOS, firmware, and driver enablement using virtual platforms.
• Validate models against RTL or hardware references for accuracy.
• Work with simulators like Synopsys Virtualizer, Cadence VSP, QEMU-based frameworks.
• Collaborate with architects, RTL designers, platform engineers, and performance teams to align results with goals.
• Document model features, APIs, interfaces, and workflows for internal teams.

Skills

SystemC

TLM2.0

C/C++

Computer architecture

Cycle-accurate modeling

Pre-silicon simulation

Virtual platforms

Performance analysis

Debugging in simulation

AI accelerators knowledge

Education

Bachelor's or Master's in Computer Engineering/EE/CS

Tools

Synopsys Virtualizer

Cadence VSP

QEMU

Job description

We are looking for a skilled SystemC Modeling Developer to join our Server Architecture & Performance Engineering team. In this role, you will design and develop SystemC/TLM models for next-generation Compute and AI server platforms, enabling architecture exploration, performance analysis, and pre-silicon software development. This is a high-impact opportunity to directly influence future server SOC and platform designs.

Key Responsibilities:

• Develop SystemC/TLM2.0-based functional, timing, and performance models for server subsystems (CPU, memory, I/O, accelerators, AI engines).
• Build modular, scalable models for Compute & AI workloads and integrate them into simulation frameworks.
• Perform system-level performance modeling, profiling, and bottleneck analysis across compute, memory, and accelerator paths.
• Support pre-silicon BIOS, firmware, and driver enablement using virtual platforms.
• Validate models against RTL or hardware references to ensure functionality and accuracy.
• Work with simulators such as Synopsys Virtualizer, Cadence VSP, QEMU-based frameworks, etc.
• Collaborate with architects, RTL designers, platform engineers, and performance teams to align modeling results with product goals.
• Document model features, APIs, interfaces, and usage workflows for internal teams.

Required Skills:

• Strong hands-on experience with SystemC, TLM2.0, and C/C++.
• Solid understanding of computer architecture including CPU pipelines, cache hierarchy, memory controllers, PCIe/CXL, and AI/compute subsystems.
• Experience in cycle-accurate, timing-accurate, or transaction-level modeling.
• Knowledge of pre-silicon simulation flows and virtual platform development.
• Ability to analyze performance data, interpret system behavior, and provide optimization insights.
• Strong debugging skills in complex simulation environments.

Desired Skills:

• Experience modeling AI/ML accelerators, GPUs, or heterogeneous compute units.
• Familiarity with server-class SoC architectures (x86, ARM, RISC-V).
• Exposure to firmware/BIOS bring-up using virtual models.
• Knowledge of RTL design (SystemVerilog) or hardware emulation (optional).
• Experience with performance tools, trace-driven analysis, or workload modeling.
• Understanding of high-speed interfaces (PCIe, CXL, NVMe, Ethernet).

Qualification:

• Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, Computer Science, or related field.
• 8+ years of experience in SystemC/TLM modeling, pre-silicon simulation, or architectural modeling for semiconductor/server platforms.