Superconducting IC Layout Engineer — Tapeout & Growth

Great Sky; Boulder (CO); Hybrid; USD 110,000 - 170,000; Full time

Benefits offered by this job

Equity ownership

Employer-matched 401(k)

Health, dental, vision, life insurance

Flexible PTO

Learning and conference support

Job summary

Great Sky seeks an integrated circuit layout engineer to optimize superconducting circuitry for our AI hardware platform. You will help realize efficient layouts for device cells and neural-network blocks, with emphasis on area, parasitics, and manufacturability.

We value 3+ years in IC layout, Cadence Virtuoso, Python scripting, and experience toward a tapeout. Hybrid/onsite collaboration with fabrication teams and external foundries is supported.

Qualifications

• Bachelor’s degree in electrical/ computer engineering, physics, or related field or equivalent experience.
• 3+ years of IC layout engineering experience in semiconductor or superconducting domains.
• Experience with layout tools and formats such as Cadence Virtuoso, KLayout, Calibre, GDSII/OASIS, PCells, DRC/LVS.

Responsibilities

• Create layouts for superconducting device cells, reusable blocks, and neural-network circuits.
• Optimize layouts for area, parasitics, device performance, manufacturability, and scaling.
• Extend and improve parametric/script-based layout engine using Python.
• Support post-layout extraction and verification of superconducting circuits.
• Collaborate with fabrication team and external foundries for chip manufacturing.

Skills

IC layout engineering

Python scripting

Post-layout extraction

tapeout / hierarchical layout

Education

Bachelor’s degree in EE/CE/Physics

Tools

Cadence Virtuoso

KLayout

Calibre

GDSII/OASIS

PCells

DRC/LVS workflows

Job description

Great Sky seeks an integrated circuit layout engineer to optimize superconducting circuitry for our AI hardware platform. You will help realize efficient layouts for device cells and neural-network blocks, with emphasis on area, parasitics, and manufacturability.

We value 3+ years in IC layout, Cadence Virtuoso, Python scripting, and experience toward a tapeout. Hybrid/onsite collaboration with fabrication teams and external foundries is supported.