Senior Photonic IC Layout Engineer — AI-Driven Tape-out

Nvidia Corporation; Santa Clara (CA); On-site; USD 132,000 - 235,750; Full time

Benefits offered by this job

Equity and benefits

Job summary

Nvidia Corporation is hiring a Senior Photonic Layout Design Engineer located in Santa Clara, California. This role involves the design and verification of advanced photonic integrated circuits, requiring expertise in layout techniques and a deep understanding of semiconductor fabrication.

The ideal candidate should have a comprehensive background in analog circuit layout and extensive experience in using Cadence Virtuoso and verification tools. Strong programming skills and a collaborative attitude are necessary for success in this position.

This position offers a competitive salary range of $132,000 to $235,750 depending on experience, along with equity and benefits.

Qualifications

• At least 6+ years of hands-on, full-chip layout design experience in semiconductor, analog, or silicon photonics industries.
• Proven expertise with verification suites for layout checks.
• Ability to optimize workflows using industry best practices.

Responsibilities

• Take ownership of the physical design and verification of photonic integrated circuits.
• Lead complex layout designs for waveguides and mixed-signal functions.
• Execute rigorous post-layout verification across multiple versions.
• Develop and implement AI-assisted design methods.

Skills

Deep technical understanding of advanced node semiconductor fabrication

Automation capabilities

High-density chip designs

Proficiency in Cadence Virtuoso

Strong programming skills (Python, SKILL, Perl, TCL, C++)

Education

BS, MS, or Ph.D. in Electrical Engineering, Physics

Tools

Cadence Virtuoso

Calibre

Hercules

ICV

Dracula

Primeyield

Job description

Nvidia Corporation is hiring a Senior Photonic Layout Design Engineer located in Santa Clara, California. This role involves the design and verification of advanced photonic integrated circuits, requiring expertise in layout techniques and a deep understanding of semiconductor fabrication.

The ideal candidate should have a comprehensive background in analog circuit layout and extensive experience in using Cadence Virtuoso and verification tools. Strong programming skills and a collaborative attitude are necessary for success in this position.

This position offers a competitive salary range of $132,000 to $235,750 depending on experience, along with equity and benefits.