Static Timing Analysis Engineer - Wireless SoC Design

Qualcomm; Santa Clara (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Qualcomm in Santa Clara, CA is seeking an STA Engineer to lead static timing analysis for advanced wireless SoCs. You will own timing closure, develop constraints, perform timing signoff, and optimize paths across process, voltage, and temperature corners.

Collaborating with RTL, physical design, and verification teams, you will debug violations, push for higher performance, and help ensure robust silicon that meets challenging high-speed wireless requirements.

Qualifications

• Experience in static timing analysis for ASIC/SoC designs.
• Strong understanding of digital design and clocking.
• Experience with constraints and timing signoff across multiple corners.

Responsibilities

• Own timing closure for complex digital designs, including constraint development, timing signoff, and path optimization across multiple process, voltage, and temperature corners.
• Partner with RTL, physical design, and verification teams to debug violations, improve performance, and ensure robust silicon.

Skills

STA expertise

Digital design knowledge

Clock synchronization

Wireless high-speed

Tools

STA tools

Job description

Qualcomm is seeking an STA Engineer to drive static timing analysis for advanced wireless SoCs in our Telecommunications & Media portfolio. You will own timing closure for complex digital designs, including constraint development, timing signoff, and path optimization across multiple process, voltage, and temperature corners. Partner with RTL, physical design, and verification teams to debug violations, improve performance, and ensure robust silicon. Ideal candidates bring strong STA tool expertise, solid understanding of digital design and clocking, and a passion for pushing the limits of high‑speed, low‑power wireless technologies.