Circuit Design Automation Engineer

Socket.dev; Austin (TX); On-site; USD 180,000 - 260,000; Full time

Job summary

Socket.dev in Austin is seeking a Custom Design Automation engineer to lead automation of memory analysis and SRAM design flows within our digital design team. You will collaborate across disciplines to bring functional, scalable memory-rich SoCs to customers quickly, while improving flows and tooling.

Responsibilities include automating analysis, building memory compiler tech, debugging for IP users, and developing QA checks for SRAM and registers.

Qualifications

• BS and at least 10 years of relevant industry experience.
• Fundamentals in custom transistor-level circuits and SRAM designs.
• Strong programming skills in Perl, Python, TCL, and Shell.

Responsibilities

• Automate custom analysis flows to fix design margins.
• Build and maintain memory compiler technologies for large SoC memory arrays.
• Debug and provide quick solutions for digital IP designers and users.
• Define and develop QA checks to verify EDA views of SRAM and register files.
• Collaborate with design and CAD teams to optimize design flows, timing, and power for SRAM designs.
• Apply machine learning to optimize flows and QA checks.

Skills

SKILL

Perl

Python

TCL

Shell

Education

BS in Electrical Engineering or related field

Tools

Memory compiler tech

EDA tools

Circuit simulators

Job description

DESCRIPTION

Imagine yourself at the center of our hardware development effort. Where you will collaborate with all disciplines, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new ideas, as well as work with a team of talented engineers. As a Custom Design Automation engineer for digital design team, you will perform the following:

• Responsible for working on initiatives to automate custom analysis flows for fixing the design margins
• Build and maintain memory compiler technologies to facilitate in creating memory arrays in large SoC designs
• Debug and provide quick solutions for digital IP designers and/or users.
• Define and develop QA checks to verify EDA views of SRAM and register files.
• Collaborate with design and CAD team to optimize design flows and timing / power methodologies for SRAM designs
• Apply machine learning to optimize flows and QA checks

MINIMUM QUALIFICATIONS

BS and a minimum of 10 years of relevant industry experience.

PREFERRED QUALIFICATIONS

• We are looking for applicants with fundamentals in custom transistor level circuits and SRAM designs
• Efficient programming skills in languages like: SKILL, Perl, Python, TCL, Shell.
• Ability to work collaboratively with the circuit team to define and maintain design flows and tools.
• Solid understanding of industry standard circuit simulator and debug tools, and STA tools.
• Knowledge of timing, power, noise and EMIR analysis
• Ability to provide automations for rapid and dynamic design needs.