Staff Memory Design Engineer: AI-Driven DRAM & CMOS

Micron Technology, Inc.; Richardson (TX); Presencial; USD 120.000 - 180.000; Jornada completa

Descripción de la vacante

Micron Technology, Inc. in Richardson, Texas, is seeking a Staff Memory Design Engineer to design, simulate and optimize DRAM circuits, collaborating across global teams to deliver high-quality memory products.

You will use Cadence Virtuoso, FINESIM, HSPICE and VERILOG to model circuits, validate silicon, and drive floorplanning and performance. A BS or MS in EE and 6+ years in DRAM design are preferred.

Formación

• Coursework in CMOS Circuit Design, VLSI, and Analog Circuit Design, with understanding of device reliability and circuit floor planning.
• Proficiency with Cadence Virtuoso, and experience simulating with FINESIM, HSPICE, and VERILOG.
• Expertise in DRAM subsystem architecture, specification, operation, or design, including cross-department leadership.

Responsabilidades

• Design digital, analog, and memory core circuits, from concept to solution.
• Use AI-enabled tools for schematic editing, data collection, and layout floorplanning.
• Conduct circuit simulations and validate builds through tape-out revisions and silicon correlation.
• Collaborate across global teams to ensure manufacturability, yield, and cost targets.
• Lead design reviews and prepare status reports on progress and decisions.

Conocimientos

CMOS circuit design

VLSI

Analog circuit design

Device reliability

Floor planning

Cross-functional collaboration

Educación

BS or MS in Electrical Engineering or related field

Herramientas

Cadence Virtuoso

FINESIM

HSPICE

Verilog

Descripción del empleo

Micron Technology, Inc. in Richardson, Texas, is seeking a Staff Memory Design Engineer to design, simulate and optimize DRAM circuits, collaborating across global teams to deliver high-quality memory products.

You will use Cadence Virtuoso, FINESIM, HSPICE and VERILOG to model circuits, validate silicon, and drive floorplanning and performance. A BS or MS in EE and 6+ years in DRAM design are preferred.