Staff Layout Designer – Pathfinding

Jobtailor; Idaho; On-site; USD 120,000 - 180,000; Full time

Job summary

Jobtailor is seeking an experienced semiconductor layout engineer in Idaho to develop multidimensional layouts and detailed device drawings. The role requires leadership in block developments and data integrity verification, with an emphasis on meeting deadlines and resource planning.

The ideal candidate has 10 years in semiconductor layout, deep EDA tool proficiency (Cadence Virtuoso, Synopsys, Calibre), and strong debugging, design-rule compliance, and mentoring abilities to drive layout

Qualifications

• Bachelor's or AS in Electronics/Electrical Engineering with 10 years in semiconductor layout design.
• Expert in EDA tools Cadence Virtuoso, Synopsys, Calibre.
• Strong root-cause debugging and layout verification skills.
• Excellent communication skills (verbal and written).
• Deep understanding of design rules and delivering quality layouts.
• Experience mentoring junior engineers.

Responsibilities

• Develop and prepare multi-dimensional layouts and detailed drawings of semiconductor devices.
• Verify data integrity and lead major block developments.
• Organize logistics and resource allocations to meet deadlines.
• Mentor junior team members.
• Improve layout efficiency through automation and new methodologies.

Skills

Root-cause analysis

Physical verification

Layout optimization

Communication

Mentoring

Education

AS or Bachelor's in Electronics/Electrical Engineering

Tools

Cadence Virtuoso

Synopsys

Calibre

Job description

Responsibilities

• Develop and prepare multi-dimensional layouts and detailed drawings of semiconductor devices
• Verify data integrity and take the lead in major block developments
• Organize and prioritize logistics and resource allocations to meet scheduled deadlines
• Effectively mentor junior team members
• Contribute to the improvement of layout efficiency through automation and new methodologies

Requirements

• AS or Bachelor's in Electronics, Electrical Engineering, or a related field plus 10 years of direct experience in semiconductor layout design
• Deep working knowledge of EDA tools (i.e. Cadence Virtuoso, Synopsys, Calibre)
• Strong ability to debug problems through root-cause analysis
• Skilled in developing and applying custom layout, floor‑planning, signal‑planning and power‑planning methodologies
• Strong verbal and written communication skills
• In‑depth understanding of design rules and delivering quality layouts
• Strong physical verification analysis and debugging skills