Senior Layout Designer – Pathfinding

Jobtailor; Idaho; On-site; USD 90,000 - 130,000; Full time

Job summary

Jobtailor in Idaho seeks an experienced semiconductor layout designer to develop multi-dimensional layouts and provide detailed device drawings from schematics. You will mentor junior staff, improve layout efficiency, and lead major blocks and product revisions with cross‑functional teams across global sites.

Applicants should have an AS or Bachelor's in electronics or electrical engineering and at least 3 years of direct layout design experience, with strong skills in EDA tools and design rule

Qualifications

• AS or Bachelor’s in Electronics, Electrical Engineering, or a related field is required.
• 3 years of direct experience in semiconductor layout design.
• Deep working knowledge of EDA tools (Cadence Virtuoso, Synopsys, Calibre).
• Strong ability to debug problems through root-cause analysis.
• Skilled in developing and applying custom layout, floor-planning, signal-planning, and power-planning methodologies.
• Strong verbal and written communication skills.
• In-depth understanding of design rules and delivering quality layouts.
• Strong physical verification analysis and debugging skills.

Responsibilities

• Develop and prepare multi-dimensional layouts.
• Provide detailed drawings of semiconductor devices from schematics.
• Verify data integrity.
• Communicate effectively with other functional groups across global sites.
• Organize and prioritize logistics and resource allocations.
• Contribute to group management and technical innovation.
• Effectively mentor junior team members.
• Contribute to the improvement of layout efficiency through automation and new methodologies.
• Lead, plan, and deliver major blocks and product revisions.

Skills

Root-cause analysis

Mentoring juniors

Layout methodologies

Communication skills

Education

AS or Bachelor’s in Electronics/Electrical Engineering

Tools

Cadence Virtuoso

Synopsys

Calibre

Job description

Responsibilities

• Develop and prepare multi-dimensional layouts
• Provide detailed drawings of semiconductor devices from schematics
• Verify data integrity
• Communicate effectively with other functional groups across global sites
• Organize and prioritize logistics and resource allocations
• Contribute to group management and technical innovation
• Effectively mentor junior team members
• Contribute to the improvement of layout efficiency through automation and new methodologies
• Lead, plan, and deliver major blocks and product revisions

Requirements

• AS or Bachelor's in Electronics, Electrical Engineering, or a related field
• 3 years of direct experience in semiconductor layout design
• Deep working knowledge of EDA tools (i.e., Cadence Virtuoso, Synopsys, Calibre)
• Strong ability to debug problems through root‑cause analysis
• Skilled in developing and applying custom layout, floor‑planning, signal‑planning, and power‑planning methodologies
• Strong verbal and written communication skills
• In‑depth understanding of design rules and delivering quality layouts
• Strong physical verification analysis and debugging skills

Core Competencies

Demonstrates expertise in semiconductor layout design, utilizing EDA tools for effective debugging and verification. Capable of mentoring team members while driving innovation and efficiency in layout methodologies.

Tools & Technologies

• Cadence Virtuoso
• Synopsys
• Calibre