Staff IC Verification Engineer

8413 LSI Corporation; Fort Collins (CO); On-site; USD 110,000 - 176,000; Full time

Benefits offered by this job

Medical plan

Dental plan

Vision plan

401(k) with company match

Employee Stock Purchase Program

Employee Assistance Program

Paid holidays

Paid time off

Job summary

Broadcom, Inc. in Fort Collins, CO, seeks an experienced verification engineer to develop verification environments with SystemVerilog and UVM, and to design verification components such as sequences, agents, and scoreboards.

You will implement coverage and assertions and develop random and directed tests to close coverage gaps. The role requires deep HDL knowledge, experience with constrained random environments, and proficiency in C++/Java.

Qualifications

• Verified expertise in HDL languages Verilog/VHDL and SystemVerilog.
• Experience with constrained random verification environments (UVM/OVM/VMM).
• Proficiency with HDL simulators and debugging techniques.
• Strong OO programming knowledge (C++, Java) and experience.
• Ability to think critically and lead complex engineering problems.
• Independent contributor who can work in a matrix organization.
• US work authorization is required; no immigration sponsorship.

Responsibilities

• Develop verification environments using SystemVerilog and UVM.
• Design verification classes such as UVM sequences, agents, scoreboards, and models.
• Implement coverage and assertions in SystemVerilog.
• Create random and directed test cases to close coverage gaps.
• Analyze and debug simulation failures and coverage results.

Skills

Verilog/SystemVerilog

UVM/OVM/VMM

HDL simulators

C++

Java

Communication skills

Leadership

Independent thinking

Education

Bachelor's in EE/CE/CS with 8+ years related experience; or Masters in EE/CE/CS with 6+ years related experience

Tools

ModelSim

VCS

Job description

Responsibilities

• Verification environment development using modern verification techniques (System Verilog and UVM)
• Designing verification classes such as UVM sequences, agents, scoreboards, and behavioral models
• Implementing coverage and assertions using System Verilog
• Developing random & directed test cases to close coverage
• Analyzing and debugging simulation failures, as well as analyzing coverage results.
• Candidate must be a highly productive individual contributor with demonstrated technical capability in system and sub-block level verification.

Skills & Experience

• Excellent communication and interpersonal skills
• Experience communicating in a matrix organization to achieve common goals
• Demonstrated expertise in HDL languages Verilog/VHDL and SystemVerilog
• Experience designing in constrained random environments using UVM, OVM, or VMM
• Experience running and debugging using HDL simulators
• Demonstrated familiarity with OOP languages (C++, Java, etc.) and Proficient with OOP techniques
• Demonstrated critical thinking to conceive and develop innovative solutions to solve complex engineering problems
• Demonstrated leadership skills
• Act independently to determine methods and procedures on new or special assignments
• Must have legal authorization to work in the US.
• This position does not have funding to support company-sponsored immigration support

Education

• Bachelors in EE, CE, or CS and 8+ years of related experience; or Masters degree in EE, CE, or CS and 6+ years of related experience

Compensation and Benefits

The annual base salary range for this position is USD 109,700.00 To USD 175,500.00.

You’ll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards.

• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company paid holidays
• Paid sick leave and vacation time
• Paid Family Leave and other leaves of absence

All subject to relevant plan documents and award agreements.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.