Design Verification Engineer

Broadcom; San Jose (CA); On-site; USD 150,000 - 210,000; Full time

Benefits offered by this job

Equity grants

Annual bonus

401(k) with company match

Employee Stock Purchase Program (ESPP)

Job summary

Broadcom, Inc. in San Jose, CA, is seeking experienced ASIC verification engineers to join a high-performance design team.

You will work on state-of-the-art subsystem development, focusing on verification environments, UVM agents, and behavioral models to meet stringent customer requirements. The role emphasizes SystemVerilog verification, DV methodologies, and strong debugging skills, with collaboration across interfaces to design teams and verification teams.

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering, or equivalent.
• 12+ years of relevant industry experience.
• Fluent knowledge of RTL verification methodologies including SystemVerilog.
• Strong experience in ASIC design verification flows and DV methodologies.
• Strong working knowledge of OVM/UVM, C/C++, Perl, and scripting.
• Excellent debugging and independent problem-solving abilities.
• Strong verbal and written communication skills and teamwork.

Responsibilities

• Verification environment development using SystemVerilog and UVM.
• Designing verification components such as UVM agents and behavioral models.
• Implementing coverage and assertions using SystemVerilog.
• Developing random and directed test cases against the specification.
• Analyzing and debugging simulation failures and coverage results.

Skills

SystemVerilog

UVM

RTL verification

C/C++

Perl

Scripting

OVM

Debugging

Communication

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Emulators

FPGA prototyping

DV tools

Job description

Please Note:1. If you are a first time user, please create your candidate login account before you apply for a job.2. If you already have a Candidate Account, please Sign-In before you apply.Job Description:The ASIC Product Division at Broadcom, a leading supplier of state-of-the-art SoC and embedded IP, is looking for qualified individuals to work in SoC and IP development programs. The candidate will be joining a high performance design team responsible for state-of-the-art subsystem development to meet customer requirements.Responsibilities include:Verification environment development using modern verification techniques (System Verilog and UVM)Designing verification components such as UVM agents, and behavioral modelsImplementing coverage and assertions using System VerilogDeveloping random and directed test cases against the specificationAnalyzing and debugging simulation failures, as well as analyzing coverage resultsJob Requirements:A Bachelor’s Degree in Electrical and Electronic Engineering, Computer Science, or equivalent12+ year’s relevant industry work experience.Experience in verifying designs at system level and block level.Fluent knowledge of RTL verification methodologies including System Verilog.Strong experience in ASIC design verification flows and DV methodologiesStrong working knowledge of object oriented verification languages (OVM, UVM, etc.), C/C++, Perl, and scripting skills.Strong and independent design debugging capability.Strong verbal and written communication skills. Must be comfortable working in a team environment with verification team and design team members.Demonstrated ability to analyze and resolve complex verification trade-off scenarios.Highly productive individual contributor with a demonstrated technical capability in system and sub-block level verificationMust have legal authorization to work in the USThe candidate should have expertise in some (or preferably all) of the following areas:Experience with hardware design and debug, C++/SystemC and other programming languages are a strong plus.Experience working with Emulators and FPGA based prototyping is a plus.Familiarity with overall chip design methodologies and toolsKnowledge of CPU, DDR, Bus Protocol, Network Protocol or DSP design preferredCompensation and BenefitsThe annual base salary range for this position is USD To USDAs a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.