Staff Engineer, DRAM & HBM Architecture

Samsung Semiconductor; San Jose (CA); On-site; USD 163,000 - 253,000; Full time

Benefits offered by this job

Medical/Dental/Vision

401k

Onsite Café and gym

Job summary

Samsung Semiconductor seeks an experienced DRAM design expert for our San Jose team. You will lead architecture development for next‑gen DRAM, including HBM, floorplanning, and DFT strategies, while coordinating with product managers and engineers to align with strategic roadmaps.

Ideal candidates bring 10+ years in memory design, strong proficiency with design software and statistical tools, and a track record of reducing power consumption in high‑density memory products.

Qualifications

• Bachelor's with 10+ years of industry experience in DRAM or related field.
• Memor y design knowledge and proven track record.
• Proficient with design software and statistical analysis tools.

Responsibilities

• Develop DRAM architecture and optimize floorplan for next generation DRAM.
• Lead design specification, performance analysis and test planning.
• Interact with internal and external customers for requirements and feedback.
• Develop ROW/Column Bank architectures and related test modes.
• Reduce DRAM power consumption through architectural optimizations.
• Analyze electrical data and validate new core design performance.
• Develop and implement DFT architecture and methods for products.
• Plan power delivery network floor planning and optimization.
• Collaborate with product managers, engineers, and marketers to align with product vision.

Skills

DRAM design

HBM

I/O interfaces

DFT architecture

Power delivery

Cross-functional collaboration

Statistical analysis

RTL design

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree in Electrical Engineering or related field

PhD in related field

Tools

Design software

Statistical analysis tools

Job description

Samsung Semiconductor seeks an experienced DRAM design expert for our San Jose team. You will lead architecture development for next‑gen DRAM, including HBM, floorplanning, and DFT strategies, while coordinating with product managers and engineers to align with strategic roadmaps.

Ideal candidates bring 10+ years in memory design, strong proficiency with design software and statistical tools, and a track record of reducing power consumption in high‑density memory products.