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Samsung Semiconductor's DRAM Design Lab (DDL) in San Jose, CA, seeks a hardware design engineer to develop DRAM architecture, optimize floorplans, and lead design specifications. You will collaborate with internal and external teams to advance HBM-focused DRAM solutions, driving performance and reliability in mass production.
Role focuses on full chip sim checks, DFT consultation, IDD/PDN reliability analysis, and power-network optimization, with on-site daily presence at the San Jose office
Samsung Semiconductor's DRAM Design Lab (DDL) in San Jose, CA, seeks a hardware design engineer to develop DRAM architecture, optimize floorplans, and lead design specifications. You will collaborate with internal and external teams to advance HBM-focused DRAM solutions, driving performance and reliability in mass production.
Role focuses on full chip sim checks, DFT consultation, IDD/PDN reliability analysis, and power-network optimization, with on-site daily presence at the San Jose office