DRAM Architect for HBM & Power Optimization

Samsungsemiconductor

San Jose (CA)

On-site

USD 120,000 - 180,000

Full time

11 days ago
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Job summary

Samsung Semiconductor's DRAM Design Lab (DDL) in San Jose, CA, seeks a hardware design engineer to develop DRAM architecture, optimize floorplans, and lead design specifications. You will collaborate with internal and external teams to advance HBM-focused DRAM solutions, driving performance and reliability in mass production.

Role focuses on full chip sim checks, DFT consultation, IDD/PDN reliability analysis, and power-network optimization, with on-site daily presence at the San Jose office

Qualifications

  • Shows expertise in DRAM architecture and floorplanning.
  • Experience designing DFT methods and test plans.
  • Ability to analyze electrical data and validate core designs.
  • Ability to optimize DRAM power consumption and performance.

Responsibilities

  • Develop DRAM architecture and optimize floorplan for next generation DRAM.
  • Lead design specification, performance analysis and test plan.
  • Technical interactions with internal and external customers.
  • Develop ROW, Column Bank architecture design and related test modes.
  • Develop methods to reduce DRAM power consumption.
  • Analyze electrical data from Si and validate new core design architecture performance.
  • Develop and implement a DFT architecture and methodology for the product.
  • Power delivery network floor planning and optimization.

Skills

DRAM architecture
Floorplanning
DFT architecture
Power delivery
Test planning
Data analysis
Product design collaboration

Job description

Samsung Semiconductor's DRAM Design Lab (DDL) in San Jose, CA, seeks a hardware design engineer to develop DRAM architecture, optimize floorplans, and lead design specifications. You will collaborate with internal and external teams to advance HBM-focused DRAM solutions, driving performance and reliability in mass production.

Role focuses on full chip sim checks, DFT consultation, IDD/PDN reliability analysis, and power-network optimization, with on-site daily presence at the San Jose office

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