Staff Engineer, DRAM

Samsungsemiconductor; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Samsung Semiconductor's DRAM Design Lab (DDL) in San Jose, CA, seeks a hardware design engineer to develop DRAM architecture, optimize floorplans, and lead design specifications. You will collaborate with internal and external teams to advance HBM-focused DRAM solutions, driving performance and reliability in mass production.

Role focuses on full chip sim checks, DFT consultation, IDD/PDN reliability analysis, and power-network optimization, with on-site daily presence at the San Jose office

Qualifications

• Shows expertise in DRAM architecture and floorplanning.
• Experience designing DFT methods and test plans.
• Ability to analyze electrical data and validate core designs.
• Ability to optimize DRAM power consumption and performance.

Responsibilities

• Develop DRAM architecture and optimize floorplan for next generation DRAM.
• Lead design specification, performance analysis and test plan.
• Technical interactions with internal and external customers.
• Develop ROW, Column Bank architecture design and related test modes.
• Develop methods to reduce DRAM power consumption.
• Analyze electrical data from Si and validate new core design architecture performance.
• Develop and implement a DFT architecture and methodology for the product.
• Power delivery network floor planning and optimization.

Skills

DRAM architecture

Floorplanning

DFT architecture

Power delivery

Test planning

Data analysis

Product design collaboration

Job description

Please Note:

To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.

Advancing the World’s Technology Together

Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future.

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

What You’ll Do

TheDRAM Design Lab (DDL) is part of Samsung’s Memory Business Unit, the industry's technology and volume leader in DRAM, NAND Flash. DDL’s vision is to solve key problems in developing next-generation DRAM solutions, including High Bandwidth Memory (HBM). We are an integral part of Samsung’s strong R&D focus & lab innovation engine. We work closely with development teams to bring feature innovation to product roadmaps.

Come join the team that is designing HBM product, developing DRAM architecture, co-working head office and managing customer in all stages of design. You’ll focus on enhancement of full chip sim check, DFT consultation, IDD / PDN / checking reliability by developing the architecture of DRAM and optimize it for mass production.

Location: Daily onsite presence at our San Jose office in alignment with our Flexible Work policy

Job ID: 43012

• Develop DRAM architecture and optimize floorplan for next generation DRAM
• Lead design specification, performance analysis and test plan etc.
• Technical interactions with internal and external customers
• Develop ROW, Column Bank architecture design and related test modes
• Develop methods to reduce DRAM power consumption
• Analyze electrical data from Si and validate new core design architecture performance
• Develop and implement a DFT architecture and methodology for the product
• Power delivery network floor planning and optimization