Staff DRAM Architect – HBM & Power Optimization (Flexible)

Conductor; San Jose (CA); On-site; USD 163,000 - 253,000; Full time

Benefits offered by this job

Medical/Dental/Vision

401k

Onsite Café

Gym

Flexible work environment

Job summary

Samsung Semiconductor's DRAM Design Lab in San Jose seeks an experienced memory designer to advance high-performance DRAM architectures, optimize floorplans, and drive DFT and test programs. This full-time role focuses on R&D activities and collaboration with product teams.

Ideal candidates will have extensive DRAM experience and be proficient with design and verification tools. The company offers a comprehensive benefits package and on-site work in California.

Qualifications

• Experience in DRAM design and memory architectures.
• Proficiency with design software and verification tools.
• Strong analytical and problem-solving skills.

Responsibilities

• Develop DRAM architecture and optimize floorplan for next-gen devices.
• Lead design specifications, performance analysis, and test plans.
• Collaborate with cross-functional teams to align with product strategy.
• Implement DFT architecture and POWER/PDN considerations.

Skills

Memory design

DRAM I/O/interfaces

DFT design

Statistical analysis

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree in Electrical Engineering

PhD in memory/semiconductor field

Tools

Design software

Verification tools

Job description

Samsung Semiconductor's DRAM Design Lab in San Jose seeks an experienced memory designer to advance high-performance DRAM architectures, optimize floorplans, and drive DFT and test programs. This full-time role focuses on R&D activities and collaboration with product teams.

Ideal candidates will have extensive DRAM experience and be proficient with design and verification tools. The company offers a comprehensive benefits package and on-site work in California.