Staff Design Verification Engineer — Hybrid

Arm Limited; Austin (TX); On-site; USD 198,000 - 268,000; Full time

Job summary

Arm Limited is seeking dedicated design verification engineers for the Neoverse CMN project. You will help build scalable verification plans, develop SystemVerilog/UVM testbenches, and debug complex features in collaboration with architects and designers.

Hybrid work is supported, with emphasis on high-performance verification in a global team. The role requires 8+ years in verification/RTL, strong knowledge of CPU microarchitecture, and experience with constrained-random testbenches.

Qualifications

• Bachelor's, Masters or PhD in Electrical/Computer Engineering or Computer Science
• 8+ years of hands on experience in verification/RTL design
• CPU microarchitecture experience including knowledge of cache coherence, memory systems, and bus protocols (e.g. AMBA CHI, ACE)
• Previous experience in specification, creation, and debug of System Verilog/UVM constrained-random testbenches

Responsibilities

• Build and maintain detailed verification plans and strategies
• Work alongside architects and designers to debug and develop new features, balancing the needs of multiple partners in our product development cycle
• Architect and develop efficient SystemVerilog/UVM based test benches
• Design new stimulus and coverage, debug functional regression failures, and close coverage
• Develop and drive improvements in our verification methodology

Skills

SystemVerilog/UVM

Verification planning

Debugging

CPU microarchitecture

Education

Bachelor/Master/PhD in ECE/CS

Tools

SystemVerilog

UVM

Testbench development

Python

Job description

Arm Limited is seeking dedicated design verification engineers for the Neoverse CMN project. You will help build scalable verification plans, develop SystemVerilog/UVM testbenches, and debug complex features in collaboration with architects and designers.

Hybrid work is supported, with emphasis on high-performance verification in a global team. The role requires 8+ years in verification/RTL, strong knowledge of CPU microarchitecture, and experience with constrained-random testbenches.