Senior C++ FPGA Emulation Engineer (RISC-V)

SiFive, Inc.; Berkeley (CA); On-site; USD 179,000 - 219,000; Full time

Benefits offered by this job

Healthcare

Retirement plans

Paid time off

Equity

Job summary

SiFive in California is seeking a seasoned software engineer to own the C++ component of our hardware emulation framework. You will join a small team (<5 engineers) and work across the stack with FPGA RTL designers, compiler developers, and RISC-V software HW teams to accelerate software development and debugging.

The ideal candidate has 7+ years of experience building complete C++ applications, deep knowledge of concurrency, and excellent communication skills.

Qualifications

• 7+ years of experience building complete C++ applications.
• Strong knowledge of C++ concurrency and multithreading.
• Excellent written and verbal communication skills.

Responsibilities

• Develop high‑performance, multithreaded C++ applications for hardware emulation.
• Collaborate with FPGA RTL designers and compiler developers.
• Build debug tools to help co-design and debug RISC‑V hardware and software.
• Contribute to next-gen hardware emulation capacity across the stack.

Skills

C++

Multithreaded

Concurrency

Communication

Education

BS/MS/PhD in CS/CE/EE

Tools

MLIR

LLVM

FPGAs

Job description

SiFive in California is seeking a seasoned software engineer to own the C++ component of our hardware emulation framework. You will join a small team (<5 engineers) and work across the stack with FPGA RTL designers, compiler developers, and RISC-V software HW teams to accelerate software development and debugging.

The ideal candidate has 7+ years of experience building complete C++ applications, deep knowledge of concurrency, and excellent communication skills.