Staff ATE Test Engineer - SoC/TPU Test & Yield Leader

Google Inc.; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Benefits offered by this job

Equity

Job summary

Google is shaping the future of AI/ML hardware through advanced TPU technology. This role centers on defining robust silicon test solutions, architecture, and end-to-end test lifecycle in high-volume manufacturing.

You will lead cross-functional teams to ensure design-for-testability and quality across next-gen chips. You will collaborate with design, DFT, and manufacturing to deliver scalable test strategies, drive yield improvements, and support data center-grade silicon objectives for

Qualifications

• Bachelor's degree in a related field or equivalent practical experience
• 10+ years in test engineering, product engineering, or silicon quality/reliability
• Experience in ASIC/SoC test development, bring-up or debug
• Experience with scan/ATPG test development or memory BIST test development
• Experience testing IPs such as PLLs, PMRO, eFuse, and temperature sensors
• Experience with UCIE, HBM, PCIE, DDR
• Experience with ATE from Advantest and Teradyne (EXA scale, UltraFlex+)

Responsibilities

• Lead development and architectural definition of silicon test requirements
• Define strategies for SoC product NPI, bring-up, verification, and qualification
• Establish standards for post-silicon testing and cross-domain collaboration
• Mentor teams to improve test coverage and quality
• Drive test program architecture optimization and yield improvements

Skills

Test engineering

SoC test development

ASIC knowledge

Test automation

DFT/ATE strategies

Hardware verification

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Advantest EXA scale

Teradyne UltraFlex+

Load board design

Job description

Google is shaping the future of AI/ML hardware through advanced TPU technology. This role centers on defining robust silicon test solutions, architecture, and end-to-end test lifecycle in high-volume manufacturing.

You will lead cross-functional teams to ensure design-for-testability and quality across next-gen chips. You will collaborate with design, DFT, and manufacturing to deliver scalable test strategies, drive yield improvements, and support data center-grade silicon objectives for