ASIC Power Manager, ML Accelerators

Google Inc.; Sunnyvale (CA); On-site; USD 192,000 - 279,000; Full time

Benefits offered by this job

Equity

Job summary

Google seeks a Power Design Manager to lead a team designing power architecture for TPU accelerators in Sunnyvale, CA. You will direct power optimization across large SoCs and drive cross‑functional collaboration with IP vendors and software teams.

The role emphasizes ownership of power modeling, DVFS techniques, and strategies to meet aggressive power and performance targets in AI/ML hardware.

Qualifications

• Bachelor's degree or equivalent practical experience in engineering field.
• 10 years of ASIC/SoC design experience is required.
• Experience with power design, modeling, and reduction techniques.

Responsibilities

• Shape the future of AI/ML hardware acceleration and TPU technology.
• Provide technical leadership for power design teams and execute complex projects.
• Drive power architecture, design and verification for SoCs with focus on low power.
• Collaborate across IP, vendors, and internal teams to meet power goals.

Skills

Power design

Power modeling

Power optimization

TPU architecture

Leadership

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science (preferred).

Job description

corporate_fare Google place Sunnyvale, CA, USA

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.


• 10 years of experience with ASIC or SoC design.


• Experience with power design, power modeling, power architecture, or power reduction methodologies/techniques.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.


• 5 years of experience managing mid-sized ASIC/SOC design teams with focus on power design and optimization.


• Experience defining and implementing chip-wide power management architectures and designs.


• Experience in power modeling, measurement, and correlation across the pre- and post-silicon phases.


• Understanding of modern power and thermal management techniques at both the silicon and system levels (including Dynamic Voltage and Frequency Scaling (DVFS), Turboing, Thermal Management, and System-Level Tradeoffs).


• Ability to solve open-ended power and performance problems under ambiguity.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems.

As a Power Design Manager within Google's silicon team, you will help deliver solutions that have a substantive impact on the technical infrastructure that enables Google. You will provide technical leadership to a group of power design engineers in an innovative and fast‑paced environment, with a focus on ASIC power architecture, design and project execution. You will own and drive complex technical projects from the concept/planning stage through execution and closure. You will bring out the best in your team to deliver designs that work for the first time with optimal power. You will bring your knowledge and experience in large SoC power architecture and design, ability to work with IP and chip vendors and manufacturers, and ability to work across organizational boundaries to identify the right people to provide technical input and execution to deliver SoC‑centric products that are key to Google's computing infrastructure.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting‑edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world‑leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job‑related skills, experience, and relevant education or training.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems.

As a Power Design Manager within Google's silicon team, you will help deliver solutions that have a substantive impact on the technical infrastructure that enables Google. You will provide technical leadership to a group of power design engineers in an innovative and fast‑paced environment, with a focus on ASIC power architecture, design and project execution. You will own and drive complex technical projects from the concept/planning stage through execution and closure. You will bring out the best in your team to deliver designs that work for the first time with optimal power. You will bring your knowledge and experience in large SoC power architecture and design, ability to work with IP and chip vendors and manufacturers, and ability to work across organizational boundaries to identify the right people to provide technical input and execution to deliver SoC‑centric products that are key to Google's computing infrastructure.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting‑edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world‑leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job‑related skills, experience, and relevant education or training.

US: $192000 - $279000 (USD) + 20% bonus target + equity + benefits

Learn more about benefits at Google .

• Manage a power design team responsible for power architecture, power optimization and system power integration.


• Lead an experienced team, define the processes, methods and tools to continuously improve the power efficiency of the TPU designs.


• Contribute to design power modeling and drive convergence to power targets.


• Investigate, specify, and deploy architectural and microarchitectural power optimization techniques. Define best practices and methodologies to achieve low‑power RTL designs.


• Collaborate with cross‑functional software and system teams to create novel power management architectures to meet power goals.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.