Silicon Design Manager, RTL Machine Learning, Accelerator Design

Google Inc.; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Benefits offered by this job

Equity grants

Job summary

Google Inc. Sunnyvale, CA is seeking a Silicon Design Manager for RTL Machine Learning and Accelerator Design to shape the future of AI/ML hardware acceleration.

You will drive TPU architecture and verification, leading a team to deliver high-performance, low-power IP for compute cores and integration with software teams. The role emphasizes architectural feasibility, timing goals, and trade-offs for physical design closure, with cross-functional collaboration across Verification, DFT, Physical

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 10 years of experience with Chip Design, ASIC Digital Design, and SystemVerilog.
• 8 years of experience in Computer Architecture and Register-Transfer Level.
• 3 years of experience in people management and developing employees.

Responsibilities

• Lead, mentor, and manage RTL design engineers performing tasks related to IP development for Compute Cores.
• Provide technical leadership to engineers and model best design practices (i.e., micro-architecture specifications, design reviews, code reviews, design methodology).
• Serve as the primary point of contact for all design-related activities on projects. Participate with Architecture and System Design teams in architecture definition, IP area estimation, power optimization, and performance enhancements.
• Collaborate closely with cross-functional teams (e.g., Verification, Design for Test, Physical Design, and Software) to make design plans and present project status throughout the development cycle.
• Drive improvements in design methodologies, processes, and quality control measures.

Skills

People management

SystemVerilog

RTL design

ASIC design

Education

Bachelor's degree in Electrical/Computer Engineering or CS

Master's or PhD in EE/CE/CS (preferred)

Tools

DFT

Synthesis

STA

Physical Design

Verification

Job description

Silicon Design Manager, RTL Machine Learning, Accelerator Design

Share Silicon Design Manager, RTL Machine Learning, Accelerator Design

Google Sunnyvale, CA, USA

X In most instances, this position requires in-person interviews as part of the hiring process.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience with Chip Design, ASIC Digital Design, and SystemVerilog.
• 8 years of experience in Computer Architecture and Register-Transfer Level.
• 3 years of experience in people management and developing employees.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Knowledge of high performance and low-power design techniques.
• Knowledge of ASIC Verification, Design For Testing (DFT), Synthesis, Static Timing Analysis (STA), or Physical Design.

About the job

In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Silicon Design Manager, you will develop high-performance and low-power hardware to enable continuous innovations in the Tensor Processing Unit (TPUs). In this role, you will work with Architects to drive architectural feasibility, establish timing design goals, and explore trade-offs for physical design closure. You will also work with Software teams to understand and implement clocking and power management requirements.

The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits

• Lead, mentor, and manage a team of RTL Design Engineers performing tasks related to IP development for Compute Cores.
• Provide technical leadership to engineers and model best design practices (i.e., micro-architecture specifications, design reviews, code reviews, design methodology, etc.).
• Serve as the primary point of contact for all design-related activities on projects. Participate with Architecture and System Design teams in architecture definition, IP area estimation, power optimization, and performance enhancements.
• Collaborate closely with cross-functional teams (e.g., Verification, Design for Test, Physical Design, and Software) to make design plans and present project status throughout the development cycle.
• Drive improvements in design methodologies, processes, and quality control measures.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionally by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.