Staff Applications Engineer, FPGA/ASIC Prototyping

Synopsys; Mountain View (CA); On-site; USD 112,000 - 168,000; Full time

Job summary

Synopsys is seeking a Staff Applications Engineer for the HAV Solutions team to help customers deploy HAPS and ProtoCompiler in FPGA-based prototyping across SoC designs. You will troubleshoot RTL and timing issues, work with PCIe, DDR, Ethernet, and AXI IP, and collaborate with R&D, sales, and customer success to accelerate prototype bring-up and field deployments.

The role emphasizes deep technical debugging, system-level thinking, and clear communication of complex problems to customer

Qualifications

• Bachelor's or Master's in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
• 5–8 years in FPGA implementation, ASIC design, ASIC verification, FPGA prototyping, or applications engineering.
• Solid experience with FPGA synthesis, place-and-route, and timing closure using Xilinx Vivado, Intel Quartus, or similar tools.
• Working knowledge of SystemVerilog, RTL design, and verification concepts.
• Hands-on experience with at least one interface IP family such as PCIe, DDR, Ethernet, USB, or AXI.
• Scripting ability in Tcl, Python, or shell for automation and flow customization.
• Experience with Synopsys HAPS, ProtoCompiler, or other FPGA-based prototyping platforms is a strong plus.

Responsibilities

• Support customer deployments of HAPS and ProtoCompiler, covering ASIC-to-FPGA flow including partitioning, synthesis, place-and-route, timing closure, and hardware bring-up.
• Debug customer designs involving interface IP such as DDR4/DDR5, PCIe, Ethernet, or AXI.
• Reproduce and analyze technical issues reported by customers, collaborating with R&D to identify root causes and deliver solutions or workarounds.
• Develop and document methodologies for partitioning strategies, clock architecture, debug instrumentation, and bring-up procedures.
• Collaborate with Sales and Customer Success to support technical evaluations, proof-of-concept engagements, and deployment planning.
• Use Verdi, ProtoCompiler runtime debug tools, and protocol analyzers to troubleshoot RTL, netlist, timing, and hardware issues.

Skills

FPGA implementation

ASIC design

ASIC verification

FPGA prototyping

Applications engineering

SystemVerilog

RTL design

Scripting (Tcl/Python/shell)

Education

Bachelor's degree in Electrical/Computer Engineering or CS

Master's degree in related field

Tools

Xilinx Vivado

Intel Quartus

ProtoCompiler

HAPS

Verdi

Job description

Synopsys is seeking a Staff Applications Engineer for the HAV Solutions team to help customers deploy HAPS and ProtoCompiler in FPGA-based prototyping across SoC designs. You will troubleshoot RTL and timing issues, work with PCIe, DDR, Ethernet, and AXI IP, and collaborate with R&D, sales, and customer success to accelerate prototype bring-up and field deployments.

The role emphasizes deep technical debugging, system-level thinking, and clear communication of complex problems to customer