STA Engineer

Anysilicon; Austin (TX); Hybrid; USD 120,000 - 160,000; Full time

Job summary

Apple seeks an ASIC STA Engineer to join a dynamic hardware team in Austin, TX. You will lead edge IP timing activities, coordinate with multiple SOC teams, and own chip and block level timing closures throughout projects.

You will develop and maintain timing analysis methodologies, work with CAD/Flow teams to improve front-end flow, and apply industry-standard tools such as Primetime. A Bachelor's degree and strong communication skills complete your profile.

Qualifications

• Bachelor's Degree in a relevant field.
• 0 years of experience.

Responsibilities

• Lead edge IP development and coordinate with multiple SOC teams.
• Execute design and integration tasks for high-quality IP deliverables.
• Own full chip and block level timing closure and constraints throughout the project.
• Collaborate with SoC Design, Verification, DFT, Architecture, and Physical Design teams.
• Work with CAD and Flow teams to define and improve front-end design methodologies.
• Develop and maintain methodologies and flows related to timing analysis.

Skills

ASIC timing concepts

TCL

Python

Perl

Self-starter

Communication

Education

Bachelor's degree

Tools

Primetime

Synthesis

Logic equivalence checks

Job description

Join Apple as an ASIC STA Engineer and be part of a dynamic team dedicated to transforming hardware technology. This role offers the opportunity to work on innovative products that enhance customer experiences and contribute to Apple's commitment to excellence and sustainability.

Responsibilities:

• Lead edge IP development and coordinate with multiple SOC teams.
• Execute design and integration tasks for high-quality IP deliverables.
• Own full chip and block level timing closure and constraints throughout the project.
• Collaborate with SoC Design, Verification, DFT, Architecture, and Physical Design teams.
• Work with CAD and Flow teams to define and improve front-end design methodologies.
• Develop and maintain methodologies and flows related to timing analysis.

Qualifications:

• Bachelor's Degree in a relevant field.
• 0 years of experience.

Skills:

• Familiarity with ASIC design timing concepts.
• Proficient in scripting languages such as TCL, Python, and Perl.
• Exposure to STA tools like Primetime and writing timing constraints.
• Knowledge of timing corners/modes and front-end tools/methodologies such as Synthesis and Logic equivalence checks.
• Self-starter and highly motivated.
• Excellent communication skills across internal groups.