STA Engineer

Chiparama; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Chiparama in San Jose, CA seeks an experienced ASIC Implementation / STA Engineer to drive full-chip timing analysis, closure, and sign-off for advanced ASIC/SoC designs.

You will own full-chip timing sign-off across all PVT corners, develop SDC constraints for functional and test modes, and lead MMMC timing analysis with automation support. Strong scripting and collaboration with multiple engineering teams are required.

Qualifications

• 12+ years of hands-on ASIC STA and timing constraint development.
• Strong experience with timing closure using Synopsys and/or Cadence tools.
• Deep knowledge of SDC constraints and timing exceptions.
• Experience with MMMC timing analysis.
• Understanding of OCV/AOCV/POCV, crosstalk/SI, and timing derates.
• Proficiency in Tcl; Python/Perl/Shell scripting is a plus.
• Strong analytical, problem-solving, and communication skills.

Responsibilities

• Own full-chip timing sign-off and timing closure across all PVT corners.
• Develop, validate, and maintain SDC timing constraints for functional/test modes.
• Perform MMMC timing analysis.
• Analyze and resolve setup, hold, transition, recovery, and removal violations.
• Drive timing closure using OCV/AOCV/POCV, SI, and IR-drop-aware STA.
• Drive timing ECOs throughout the design cycle.
• Develop and improve STA methodologies and automation flows.
• Collaborate with PD, RTL, DFT, CAD, and other teams to achieve closure.
• Automate STA analysis, reporting, and data mining with scripting.

Skills

ASIC STA

Timing closure

SDC constraints

Tcl scripting

Python scripting

Problem solving

Communication

Tools

Synopsys PrimeTime

Cadence Tempus

Job description

We are seeking an experienced ASIC Implementation / Static Timing Analysis (STA) Engineer to drive full-chip timing analysis, timing closure, and sign-off for advanced ASIC/SoC designs.

Key Responsibilities

• Own full-chip timing sign-off and timing closure across all PVT corners.
• Develop, validate, and maintain SDC timing constraints for functional and test modes, including Scan, MBIST, and ATPG.
• Perform Multi-Mode Multi-Corner (MMMC) timing analysis.
• Analyze and resolve setup, hold, transition, recovery, and removal violations.
• Drive timing closure using OCV, AOCV, POCV, signal integrity/crosstalk, and IR-drop-aware STA methodologies.
• Drive timing ECOs throughout the design cycle.
• Develop and improve STA methodologies and automation flows.
• Work closely with Physical Design, RTL, DFT, CAD, and other engineering teams to achieve timing closure.
• Automate STA analysis, reporting, and data mining using scripting.

Required Qualifications

• 12+ years of hands-on experience in ASIC STA and timing constraint development.
• Strong experience with timing closure using Synopsys and/or Cadence tools.
• Strong knowledge of SDC constraints and timing exceptions.
• Experience with MMMC analysis and advanced timing concepts.
• Strong understanding of OCV/AOCV/POCV, crosstalk/SI, and timing derates.
• Proficiency in Tcl; experience with Python, Perl, or Shell scripting is a plus.
• Strong analytical, problem-solving, and communication skills.
• Experience working in complex ASIC/SoC development environments.

Preferred Skills

• Full-chip STA and timing sign-off.
• Advanced ASIC/SoC timing closure.
• Synopsys PrimeTime and/or Cadence Tempus.
• Functional and DFT/test-mode timing analysis.
• Timing ECO generation and implementation.
• STA flow development and automation.

Location: San Jose, CA

We are an Equal Opportunity Employer and are committed to providing equal employment opportunities to all qualified applicants and employees without regard to race, color, religion, sex, gender identity or expression, sexual orientation, national origin, age, disability, veteran status, or any other characteristic protected by applicable federal, state, or local laws. We value diversity and are committed to creating an inclusive workplace where everyone is treated with respect and has an equal opportunity to succeed.