CAD Engineer - Timing for Gate-Level Flows & Methodologies

Apple, Inc.; Jackson (TN); On-site; USD 150,000 - 278,000; Full time

Benefits offered by this job

Medical and dental coverage

Employee stock purchase plan

Relocation assistance

Discretionary bonuses or commissions

Job summary

Apple, Inc. in Tennessee is seeking a seasoned STA CAD engineer to enhance timing analysis across next-generation Apple Silicon SoCs. You will own static timing methodologies and drive flows for first-time right silicon, collaborating closely with design teams.

The role requires a BS with 3+ years, strong knowledge of STA tools, Python/Tcl scripting, and solid communication. Base pay and relocation may apply; comprehensive benefits provided.

Qualifications

• Experience with static timing analysis tools and flows.
• Proficiency in Python and Tcl scripting.
• Knowledge of STA for large high-performance SoCs.
• Understanding of noise, cross-talk, variation and timing margins.
• Knowledge of timing/SDC constraints; hands-on validation is a plus.
• Excellent communication to explain issues and drive resolutions.

Responsibilities

• Develop, maintain, and improve gate-level STA flows for Apple silicon designs.
• Collaborate with design teams to debug constraints, flow scripts, and timing closure.
• Drive STA methodology updates to boost efficiency and timing correlation.
• Create and maintain timing analysis and power-reduction scripts and methods.
• Support methodologies, tools, and flows for timing constraint verification across teams.
• Analyze timing paths to identify issues and assist post-silicon timing debug.
• Coordinate with EDA vendors to adopt new capabilities.

Skills

STA tools

Python scripting

Tcl scripting

SoC timing

Noise effects

Timing margins

SDC constraints

Strong communicator

Education

BS degree in EE/CS

Job description

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, youʼll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). Youʼll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means youʼll be responsible for crafting and building the technology that fuels Appleʼs devices. Together, you and your team will enable our customers to do all the things they love with their devices!

In this role as a member of the STA CAD team, you will be an integral part of the effort to improve the performance of Apple Silicon. You will be responsible for all aspects of static timing methodologies, addressing timing challenges on advanced tech nodes through the development of flows and methodologies used by all Apple Silicon teams in driving timing analysis and closure for first time right silicon.

Description

• Develop, maintain, and enhance existing gate-level STA flows for Apple silicon designs
• Work with design teams to understand and debug issues related to constraints, flow scripts, and timing closure
• Facilitate and drive STA methodology changes to improve overall STA flows as it relates to efficiency/productivity and silicon timing correlation
• Develop and maintain scripts and methods for timing analysis and power reduction
• Develop and support methodologies, tools, and flows used in the verification of timing constraints, drive best practices across design teams
• Analysis of timing paths to identify key issues, including post-silicon timing debug
• Work closely with EDA vendors to develop and incorporate new capabilities to solve technical problems

Preferred Qualifications

• Experience with static timing analysis tools and flows
• Understanding of programming fundamentals and concepts. Familiarity with Python and Tcl or other high level programming languages
• Familiar with STA of large high-performance SoC designs in deep sub-micron technologies
• Understanding of fundamentals in noise, cross-talk, variation and timing margins
• Knowledge of timing/SDC constraints, hands on experience in creation/validation a plus
• Good communicator who can accurately assess and describe issues to management as well as follow solutions through to completion

Minimum Qualifications

• Minimum requirement of BS and 3 years of relevant industry experience.

Pay & Benefits

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $150,400 and $277,600, and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.