STA Automation & Timing Signoff Engineer

Cadence Design Systems, Inc.; San Jose (CA); On-site; USD 106,000 - 198,000; Full time

Benefits offered by this job

401(k) plan with employer match

employee stock purchase plan

medical, dental and vision plans

paid vacation and paid holidays

Job summary

Cadence Design Systems, Inc. in California seeks a timing analysis engineer to perform static timing analysis, glitch and noise analysis using Tempus Signoff. You will execute and deliver timing and ECO flows, work with R&D and customers to enable advanced timing technologies and ensure design reliability.

You will automate flows with Perl, Tcl and Python, deliver trainings at Cadence and customer sites, and lead timing signoff campaigns on existing and new designs.

Responsibilities

• Perform static timing analysis, glitch and noise analysis using Tempus Signoff on customer designs.
• Execute and deliver on timing analysis flows and ECO flows, CAD tools and methodologies.
• Automate flows using scripting languages (Perl, Tcl, Python) to improve efficiency.
• Deliver technical trainings and seminars at Cadence and customer sites.

Job description

Cadence Design Systems, Inc. in California seeks a timing analysis engineer to perform static timing analysis, glitch and noise analysis using Tempus Signoff. You will execute and deliver timing and ECO flows, work with R&D and customers to enable advanced timing technologies and ensure design reliability.

You will automate flows with Perl, Tcl and Python, deliver trainings at Cadence and customer sites, and lead timing signoff campaigns on existing and new designs.