SSG Design Engineering Intern (Fall 2026)

Cadence; San Jose (CA); On-site; USD 48,216 - 85,411; Full time

Job summary

Cadence in San Jose, CA is seeking a Design Engineering Intern for the Silicon Solutions Group to work on Digital Design or Design Verification tasks related to the Janus NoC IP product. You will collaborate with Design, Verification, and Physical Design teams to achieve timing, area, and power goals.

Candidates are pursuing an MS/BS in Electrical Engineering or Computer Engineering, with strong fundamentals in digital design and automation scripting (Tcl, Perl, shell).

Qualifications

• Enrolled in MS/BS in Electrical Engineering, Computer Engineering, or a related field.
• Strong understanding of Digital Design and/or Design Verification fundamentals.
• Proficient with Tcl, Perl, and shell scripting.
• Excellent oral and written communication skills.
• Exposure to design automation tools is a plus.
• Internship based in San Jose, CA; local candidates preferred.

Responsibilities

• Work on RTL implementation, simulation, and timing analysis for Janus NoC.
• Assist with test plans, UVM tests, and coverage analysis; debug failures and scripting flows.

Skills

Digital Design

Design Verification

Automation scripting

Communication skills

Education

MS/BS in Electrical Engineering or related field

Tools

SystemVerilog

UVM

SVA

EDA tools

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Design Engineering Intern

The Cadence Silicon Solutions Group (SSG) is seeing rapid adoption of our industry‑leading Digital IP (intellectual Property), from processor cores and DSPs to Memory Controllers, to Network on Chip (NoC), to IO solutions. Our configurable and extensible IP solutions are designed to meet the demands of SOCs and Chiplets targeted at a wide range of applications. Our customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare.

This Design Engineering Intern position involves working on Digital Design tasks or Design Verification tasks related to the Janus NoC IP product.

• Digital Design projects involve working on aspects of the logic design of the Janus NoC. They can involve RTL implementation of a specified micro‑architecture in System Verilog, simulating and debugging RTL logic, running synthesis, place & route, and other Electronic Design Automation (EDA) tools to study and achieve timing, area, and power goals.
• Design Verification Team projects involve working on aspects of the verification of the Janus NoC. Assist with developing test plans, writing functional tests (UVM) and verification monitors (SVA) UVM/SVA monitors, debugging failures, analyzing coverage information, and scripting Design Verification flows.

The Design Engineering intern will work closely with the Design, Verification, and Physical Design teams.

Position Requirements

• Currently enrolled in an MS/BS program with a major in Electrical Engineering, Computer Engineering, or a similar field.
• Deep understanding of Digital Design and/or Design Verification fundamentals.
• Excellent automation skills using Tcl, Perl, shell scripting.
• Excellent oral and written communication skills.
• Exposure to design automation tools is a plus.
• Internship will be based in San Jose, CA. Ideal candidates should be from a local school near the office.

Salary range for California is $35/hr to $62/hr. You may also be eligible to receive incentive compensation such as bonus, equity, and benefits. Salary may vary based on qualifications, skill level, competencies, and work location.

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