Sr. Principal Software Engineer

Cadence Design Systems; Austin (TX); On-site; USD 196,000 - 364,000; Full time

Benefits offered by this job

Bonus eligibility

Equity

Medical/dental/vision plans

401(k) plan with company match

PTO and holidays

Job summary

Cadence Design Systems is seeking a highly motivated hardware engineer to work with the DFT R&D team on advanced design-for-test solutions for next‑gen SoCs.

You will design DFT hardware, test fabrics, and on‑chip networks, contributing to LBIST, MBIST, POST, IST, and other high‑coverage, low‑cost strategies while collaborating across RTL, verification, and integration teams.

Qualifications

• Strong Verilog/SystemVerilog RTL for digital hardware design and simulation.
• Hands-on coding with SystemVerilog/Verilog and scripting in Perl/Python.
• Mastery of UVM and directed testbench IP verification for quality.
• Knowledge of SoC data paths, DFT concepts, and test networks.

Responsibilities

• Design and implement advanced DFT hardware and test fabrics.
• Develop on‑chip test networks for high coverage and low cost.
• Lead architecture and verification reviews across teams.
• Coordinate IP integrations and ensure delivery milestones.

Skills

RTL Design

SystemVerilog

UVM

Python scripting

Perl scripting

Debug hardware

IP integration

Test networks

LBIST/MBIST

IST

Tools

Xcelium

JasperGold

Genus

Innovus

Tempus

Modus

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Design Systems is looking for a highly motivated hardware engineer to work with the Modus R&D engineering team in the Design-For-Test (DFT) IP business unit.

As a member of the DFT R&D team , you will design and implement advanced Design‑for‑Test (DFT) hardware, test fabrics , and on‑chip test networks used in next‑generation SoCs. You will contribute to the hardware and software development of industry‑leading test solutions such as scan compression, hierarchical test access architectures, Logic Built-In-Self-Test (LBIST), Memory Built-In-Self-Test (MBIST) , Power-On-Self-Test (POST), and In-System Test (IST). Your work will directly support high‑coverage, low‑cost test strategies across complex semiconductor designs.

Required Skills

• RTL Design & Verification
  • Strong background in Verilog/SystemVerilog RTL for digital hardware design and simulation
  • Hands-on coding and automation skills using SystemVerilog/Verilog, plus scripting with Perl and Python
  • Mastery of UVM and directed testbench IP verification, including test planning, coverage closure, debug, and working with verification teams to drive quality
  • Knowledge of network structures and method for communicating data across an SoC
• Full-Flow Development & Integration
  • Proven experience developing complex reusable IPs from architecture through delivery
  • Strong experience with synthesis, lint, CDC/RDC, formal checks, timing closure, physical design, and signoff workflows
  • Ability to manage internal and third-party/services IP integrations, including requirements review, interface alignment, quality checks, and delivery tracking
  • Ability to debug complex hardware issues across RTL, verification, synthesis, timing, and integration environments
  • Strong documentation skills for architecture specs, design specs, integration guides, and verification collateral
• DFT Architecture
  • Deep understanding of digital design architecture, including subsystem integration, DFT, interconnects, memory-mapped interfaces, reset/clock architecture, and low‑power design considerations
  • Strong knowledge of DFT requirements for SoCs, including scan, MBIST, LBIST, POST, IST, IJTAG, test access architecture, and design‑for‑testability tradeoffs
  • Knowledge of DFT IP concepts, hardware, and test network communication
• Project Ownership & Team Communication
  • Experience leading design reviews, architecture reviews, microarchitecture reviews, and implementation readiness reviews
  • Strong project execution and project management skills, including planning, dependency tracking, risk management, milestone ownership, and cross‑functional coordination
  • Ability to mentor senior and junior engineers and provide technical leadership across teams
  • Good communication skills with a development team spread across multiple locations
  • Prior experience with large software development projects is highly recommended

Preferred Skills

• Experience with ISO 26262 functional safety concepts, including safety mechanisms, diagnostic coverage, safety requirements, and ASIL-oriented design flows
• Exposure to security‑aware hardware design, including secure boot concepts, access control, lifecycle management, key handling, or secure debug
• Experience with automotive, industrial, AI, or hyperscaler‑class IP development
• Familiarity with Cadence flows such as Xcelium, JasperGold, Genus, Innovus, Tempus, Modus, and related signoff/debug environments
• Experience driving IP maturity through reusable methodology, quality metrics, and scalable infrastructure

The annual salary range for California is $196,000 to $364,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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