Sr. Staff Engineer, SoC Design Verification

Tenstorrent; Boston, Santa Clara (MA, CA); Hybrid; CAD 138,000 - 691,000; Full time

Job summary

Tenstorrent is seeking a Sr. Staff Design Verification Engineer to lead end-to-end DV efforts for our CPU and AI compute platforms. The role is hybrid and based out of Boston, Toronto, Ottawa or Santa Clara, with flexibility for various experience levels during interview.

Lead the development of DV strategies, build advanced simulation environments and drive test plans to closure. You will mentor engineers and leverage AI tools to accelerate verification workflows, shaping scalable DV practices

Qualifications

• Lead end-to-end DV strategies for CPU and AI accelerator blocks.
• Build and maintain advanced simulation environments using SV-UVM, C/DPI and Cocotb.
• Mentor junior DV engineers and drive test plans to closure.

Responsibilities

• Lead development and execution of end-to-end DV strategies for CPU and AI accelerator blocks & chiplets.
• Drive test plan ownership including coverage analysis and regression management.
• Collaborate with design, architecture, post-silicon and software teams to review plans and debug issues.
• Support emulation and multi-chip verification flows where applicable, optimizing for scalability.
• Mentor junior DV engineers, sharing expertise in verification flows and leveraging AI-assisted tools.

Skills

CPU verification

Test plan ownership

Mentoring

AI tools optimization

Tools

SV-UVM

C/DPI

Cocotb

Job description

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
We are looking for a Sr. Staff Design Verification Engineer to lead end-to-end verification efforts for our advanced CPU and AI compute platforms. This role is ideal for seasoned engineers with deep expertise in CPU verification who excel at driving complex test plans to closure, mentoring teams, and leveraging modern AI tools to accelerate innovation.
This role is hybrid, based out of Boston, Toronto, Ottawa or Santa Clara.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Proven track record leading end-to-end CPU verification across processor cores, caches, interconnects, interrupts, MMU/IOMMU, and cache coherency protocols, with multi-chip and emulation experience a plus.
• Expert in creating comprehensive test plans and building simulation testbenches using SV-UVM, C/DPI, and Cocotb.
• Skilled in managing high-volume regression execution, complex failure triage, and driving test plans and coverage metrics to closure.
• Experienced leader and mentor dedicated to guiding junior engineers and fostering verification best practices across teams.
• Proficient in leveraging modern AI tools like Copilot, Cursor, Claude, Gemini, and ChatGPT to optimize verification workflows.

What We Need

• Lead the development and execution of end-to-end DV strategies for CPU and AI accelerator blocks & chiplets, ensuring robust coverage and sign-off.
• Build and maintain advanced simulation environments using SV-UVM, C/DPI, Cocotb, and other methodologies to verify complex designs.
• Drive test plan ownership, including coverage analysis, regression management, triage, and closure for multi-block CPU subsystems.
• Collaborate with design, architecture, post silicon and software teams to review plans and debug issues.
• Mentor junior DV engineers, sharing expertise in verification flows and leveraging AI-assisted tools; support emulation and multi-chip verification flows where applicable, optimizing for scalability and efficiency.

What You Will Learn

• How large-scale AI SoCs are architected, integrated, and brought to silicon.
• How verification choices directly impact design performance, power, and overall silicon success.
• How to build and scale DV flows supporting cutting-edge compute architectures.
• How to use AI to increase your productivity
• How to integrate cross-functional workflows across design, DV, physical, and firmware teams.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.