Sr. RFIC Layout Designer (RFIC Engineering)

United States Digital Space LLC; Palo Alto (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

United States Digital Space LLC is seeking a Sr. RFIC Layout Designer to join our advanced IC layout team in California.

You will collaborate with IC designers and chip leads to plan floor layouts, ensure robust power/ground networks, and optimize matching while minimizing parasitics for high-frequency RF blocks. You will estimate schedules, perform DRC/ER/LVS checks, and coordinate with EDA vendors to trial new tools.

Qualifications

• Bachelor’s degree in electrical or computer engineering with 5+ years of IC layout experience, or 8+ years of relevant layout experience in lieu of degree.
• Experience in layout of RF and analog blocks with attention to matching and minimizing parasitics.
• Strong communication and ability to work independently on challenging problems.

Responsibilities

• Determine chip floor plan with power/ground distribution and pad locations.
• Estimate layout schedule and flag complexity early.
• Layout RF and analog blocks, minimize parasitics and ensure matching.
• Perform DRC/ER and LVS checks and fix errors.
• Integrate top-level layout with ESD structures and finalize tape-out.
• Collaborate with EDA vendors to trial new tools.
• Create guides to share layout techniques with the team.

Skills

Analog layout

Advanced nodes (22nm-5nm)

RF block layout (LNA/VCO/mixers)

Shell scripting

Python

Revision control

Circuit design understanding

Linux

Communication skills

Independent work

Education

Bachelor’s degree in Electrical or Computer Engineering

8+ years IC layout experience in lieu of degree

Tools

GDSII tools

EDA tools

Job description

SR. RFIC LAYOUT DESIGNER (RFIC ENGINEERING)

At the company we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best‑class engineers to help maximize Starlink’s utility for communities and businesses around the globe.

RESPONSIBILITIES

• Work with the integrated circuit designers and chip leads to determine the chip floor plan; this includes strategies for power and ground distribution as well as working with packaging engineer to determine pad locations
• Accurately estimate the schedule for the layout work and identify areas of complexity that need early investigation
• Perform layout of custom RF and analog circuit blocks with attention to matching and minimizing parasitic capacitance in the layout
• Perform design rule checking, electrical rule checking and layout versus schematic checks and resolve errors
• Perform top‑level layout integration with electrostatic discharge structures and pad assembly and perform final tape out (including density fill, running design for manufacturability checks and sharing GDS with the foundry)
• Work with EDA suppliers to trial new tools and features
• Generate guides and demos for others in the team to showcase improvements in layout technique

BASIC QUALIFICATIONS

• Bachelor’s degree in electrical or computer engineering and 5+ years of professional experience as an IC layout designer; OR 8+ years of professional experience with integrated circuit layout design in lieu of a degree

PREFERRED SKILLS AND EXPERIENCE

• Strong analog layout skills
• Experience in advanced node IC layouts such as 22nm, 16nm, 7nm, 5nm or below
• Experience in layout of circuits with frequencies up to 50GHz
• Experience in layout of sensitive RF blocks such as low noise amplifiers, voltage controlled oscillators and mixers
• Experience with skill programming
• Experience with shell scripting, Perl, Python or similar language
• Experience managing revision control systems
• Experience with circuit design
• Understanding of layout considerations for device matching, coupling and noise isolation
• Working knowledge of Linux
• Excellent communication skills (both oral and written) are required
• Able to work independently on challenging problems

ADDITIONAL REQUIREMENTS

• Must be willing to work extended hours and weekends as needed to meet critical milestones

ITAR REQUIREMENTS

• To conform to U.S. Government export regulations, applicant must be (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

the company is an Equal Opportunity Employer; employment with the company is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of the company’s affirmative action plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to [e-mail].