RFIC Layout Designer (RFIC Engineering)

United States Digital Space LLC; Palo Alto (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

United States Digital Space LLC is seeking an RFIC Layout Designer to join our RFIC engineering team. You will collaborate with IC designers to plan chip floor layouts, optimize power/ground networks, and address parasitics in RF/analog blocks.

The role requires strong analog layout skills, experience with 50GHz+ circuits, and proficiency in Python/Perl scripting, Linux, and version control. Willingness to extend hours to meet milestones and work on-site in California.

Qualifications

• Bachelor’s degree in electrical or computer engineering or 1+ years of pro IC layout exp; OR 3+ years of pro IC layout exp in lieu of degree.
• Strong analog layout skills and experience with advanced node IC layouts.
• Experience with circuits up to 50GHz and RF block layouts.
• Experience with shell scripting, Python or Perl; Linux familiarity.
• Excellent verbal and written communication; ability to work independently.

Responsibilities

• Determine chip floor plan with IC designers and chip leads, including power/ground strategies and pad locations.
• Estimate schedule for layout work and identify complex areas early for investigation.
• Perform layout of RF and analog blocks with attention to matching and minimizing parasitic capacitance.
• Conduct DRC/EQ checks and LVS; resolve layout vs schematic discrepancies.
• Top-level layout integration with ESD structures and pad assembly; perform final tape out and density fill.
• Collaborate with EDA suppliers to trial new tools and features.
• Generate guides and demos to showcase layout technique improvements.

Skills

Analog layout

RF layout

High-frequency design (50GHz)

IC design experience

Scripting (Python, Perl)

Linux

Version control

Communication skills

Education

Bachelor’s degree in electrical or computer engineering

3+ years of IC layout design experience in lieu of degree

Tools

GDSII

EDA tools

Job description

the company was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today the company is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

RFIC LAYOUT DESIGNER (RFIC ENGINEERING)

At the company we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe.

RESPONSIBILITIES:

• Work with the integrated circuit designers and chip leads to determine the chip floor plan; this includes strategies for power and ground distribution as well as working with packaging engineer to determine pad locations
• Accurately estimate the schedule for the layout work and identify areas of complexity that need early investigation
• Perform layout of custom RF and analog circuit blocks with attention to matching and minimizing parasitic capacitance in the layout
• Perform design rule checking, electrical rule checking and layout versus schematic checks and resolve errors
• Perform top-level layout integration with electrostatic discharge structures and pad assembly and perform final tape out (including density fill, running design for manufacturability checks and sharing GDS with the foundry)
• Work with EDA suppliers to trial new tools and features
• Generate guides and demos for others in the team to showcase improvements in layout technique

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical or computer engineering and 1+ years of professional experience as an IC layout designer; OR 3+ years of professional experience with integrated circuit layout design in lieu of a degree

PREFERRED SKILLS AND EXPERIENCE:

• Strong analog layout skills
• Experience in advanced node IC layouts such as 22nm, 16nm, 7nm, 5nm or below
• Experience in layout of circuits with frequencies up to 50GHz
• Experience in layout of sensitive RF blocks such as low noise amplifiers, voltage controlled oscillators and mixers
• Experience with skill programming
• Experience with shell scripting, Perl, Python or similar language
• Experience managing revision control systems
• Experience with circuit design
• Understanding of layout considerations for device matching, coupling and noise isolation
• Working knowledge of Linux
• Excellent communication skills (both oral and written) are required
• Able to work independently on challenging problems

ADDITIONAL REQUIREMENTS:

• Must be willing to work extended hours and weekends as needed to meet critical milestones

ITAR REQUIREMENTS:

• To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

the company is an Equal Opportunity Employer; employment with the company is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of the company’s Affimitive Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to [e-mail].