Sr Principal Engineer, Design Technologist

Metric Geo; Dallas (TX); On-site; USD 180,000 - 240,000; Full time

Job summary

Metric Search partners with a world-renowned semiconductor organization to hire a Sr. Principal Engineer who will lead the Physical Design Technology Team and influence how next-generation SoCs are designed and built.

You will translate process technology capabilities into design guidelines and methodology improvements, delivering best-in-class PPA, DFM, and yield. This is a strategic role shaping EDA strategy and acting as the glue between process, design, and product functions.

Qualifications

• 15+ years in SoC design or physical design
• Experience with advanced-node fabrication and PDK
• Experience solving timing, power, and signal integrity on modern chips
• Proficient with major EDA toolsets (Cadence, Synopsys, Siemens)

Responsibilities

• Own technology benchmarking and build standardized metrics
• Collaborate with architecture, RTL, and physical design to ground decisions in process reality
• Set design methodology and sign-off strategy for advanced nodes
• Advance EDA flow improvements across synthesis, P&R, timing, power, and verification

Skills

SoC design

Physical design

EDA methodology

Process integration

Timing/power/SPA

Tools

Cadence

Synopsys

Siemens

Job description

Metric Search are exclusively partnering with a world-renowned semiconductor organization ($5B+ revenue per annum), who are seeking to hire a Sr. Principal Engineer to lead their Physical Design Technology Team, shaping how the next generation of SoCs get designed and built.

They are seeking someone to translate process technology capabilities into design guidelines and methodology improvements that deliver best in class PPA, DFM, and yield across advanced process nodes.

This is a great opportunity to join a leading organisation with the chance to define next generation design methodology, shape the company's EDA strategy, and act as the technical glue between process, design, and product functions.

Responsible for:

• Own technology benchmarking efforts and build standardized metrics for comparing node options against each other
• Sit alongside architecture, RTL, and physical design teams to keep design decisions grounded in process reality
• Set the design methodology and sign off strategy for advanced nodes, balancing performance targets against manufacturability
• Push forward EDA flow improvements across synthesis, place & route, timing, power, and verification

Requirements:

• 15+ years in SoC design, physical design, EDA methodology, or process integration, including senior technical roles
• Strong grasp of advanced-node fabrication, PDK development, and how process and design interact
• Practical experience navigating timing, power, and signal integrity challenges on modern chips
• Comfortable working with major EDA toolsets (Cadence, Synopsys, Siemens, or similar)