Senior RTL Engineer/Lead

MediaTek; Austin (TX); On-site; USD 152,400 - 254,500; Full time

Benefits offered by this job

Comprehensive health insurance

401(k)

Paid time off (PTO)

Performance bonus

Job summary

MediaTek in Austin is seeking a Senior RTL Design Engineer to lead RTL development for complex IP and ARM CPU subsystems. The role involves defining micro-architecture, ensuring RTL quality, and collaborating with worldwide teams. The ideal candidate has 8+ years of experience in RTL design, strong skills in SystemVerilog and Verilog, and a significant background in ARM CPU architecture. The position offers a competitive salary and comprehensive benefits including health insurance and a 401(k).

Qualifications

• 8+ years of industry experience in RTL design of complex IP and/or CPU subsystems.
• Proven experience across front-end quality flows: Lint, CDC, LEC/equivalence.
• Strong understanding of high-performance ARM CPU architecture.

Responsibilities

• Define micro-architecture for complex IP blocks and ARM CPU subsystems.
• Develop high-quality RTL and perform synthesis for IP and CPU subsystems.
• Run RTL quality checks and ensure RTL is robust and signoff-ready.

Skills

RTL coding and integration (SystemVerilog/Verilog)

Strong debugging and scripting skills (e.g., Perl, Python, Tcl)

Collaboration with cross-functional teams

Understanding of ARM CPU architecture

Education

Bachelor’s or Master’s degree in Computer Engineering, Electrical/Electronic Engineering

Job description

Job Description

MediaTek is a global fabless semiconductor industry leader, providing solutions from the edge to the cloud and powering over 2 billion connected devices every year. Established in 1997, our leading‑edge technologies keep the world connected and enhance everyday life. At the forefront of innovation, MediaTek drives advancements in transformative technologies such as AI, 5G/6G, and Wi‑Fi 8. Our high‑performance, power‑efficient solutions form the foundation for a smarter, more connected world, enabling devices from smartphones, smart homes, and AI PCs to high‑performance computing, automotive, and AI data centers. As a trusted partner to the world's leading brands, we are committed to ensuring access to world‑class technology for everyone. Our dedication to accelerating AI underscores our mission to enrich the future of humanity.

About the Role

We are looking for a Senior RTL Design Engineer / Lead to own micro‑architecture, RTL development, integration, and synthesis for complex IP and ARM CPU subsystems. In this role, you will drive RTL quality, collaborate with worldwide (WW) teams on specifications and deliverables, and work closely with DV and PD teams to ensure thoroughly verified, timing‑clean designs.

Key Responsibilities

• Define micro‑architecture for complex IP blocks and ARM CPU subsystems based on high‑level specifications.
• Develop high‑quality RTL (coding and integration) and perform synthesis for complex IP and CPU subsystems.
• Run RTL quality checks (e.g., Lint, CDC, LEC/equivalence checks) and ensure RTL is robust, reusable, and signoff‑ready.
• Generate and refine timing constraints; collaborate with Physical Design teams to ensure RTL meets timing and implementation goals.
• Work with DV teams to define test plans, review coverage, and thoroughly verify RTL functionality.
• Collaborate with DFT teams to help improve test coverage and support DFT insertion requirements.
• Partner with worldwide cross‑functional teams to align on specifications, interfaces, and delivery milestones.
• Use strong debugging and scripting skills to analyze issues, automate flows, and improve design productivity.

Main Requirements and Qualifications

• Bachelor’s or Master’s degree in Computer Engineering, Electrical/Electronic Engineering, or a related field.
• 8+ years of industry experience in RTL design of complex IP and/or CPU subsystems.
• Strong understanding of high‑performance ARM CPU architecture and familiarity with recent high‑performance ARM cores.
• Expertise in RTL coding and integration (SystemVerilog/Verilog) and synthesis.
• Proven experience across front‑end quality flows: Lint, CDC, LEC/equivalence, and related checks.
• Good understanding and hands‑on experience in related domains such as DV, DFT, and timing closure.
• Ability to generate timing constraints and work closely with PD teams to achieve timing closure.
• Strong debugging and scripting skills (e.g., Perl, Python, Tcl).
• Ability to collaborate with DFT teams to enhance test coverage.
• Experience working with worldwide, cross‑functional teams and strong communication skills.

Preferred Qualifications

• Prior experience in RTL integration of ARM CPU subsystems.
• Experience with multi‑power‑domain designs and low‑power methodologies.
• Prior silicon debug experience (post‑silicon bring‑up and issue resolution).

Salary & Benefits

• Salary range: $152,400 – $254,500 annually.
• Employee may be eligible for performance bonus, short and long term incentive programs.
• Comprehensive health insurance coverage, life and disability insurance, savings plan, company‑paid holidays, paid time off (PTO), parental leave, 401(k) and more.

EEO Statement

MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation.