RTL Design / Microarchitecture Engineer

Bolt Graphics; Sunnyvale (CA); On-site; USD 160,000 - 220,000; Full time

Benefits offered by this job

100% covered Medical, Dental, & Vision premiums

Equity - Stock Options

401(k) match

Job summary

A semiconductor startup in Sunnyvale, CA is seeking an RTL Design/Microarchitecture Engineer to define and implement key components of their graphics processors. Responsibilities include developing microarchitecture specifications, designing RTL for digital blocks, and optimizing performance and power efficiency. Ideal candidates have 5-10 years in RTL design, a degree in Electrical Engineering, and experience with tools like Synopsys VCS. The role offers a competitive salary range of $160,000–$220,000 annually and benefits including 100% covered health insurance and stock options.

Qualifications

• 5–10 years of experience in RTL design and microarchitecture.
• Strong understanding of FSMs, pipelines, caches, and memory interfaces.
• Experience working in ASIC/SoC development environments.

Responsibilities

• Define and develop microarchitecture specifications.
• Design RTL for complex digital blocks.
• Drive performance, power, and area optimizations at the microarchitecture level.
• Collaborate with verification teams for coverage and design correctness.
• Support IP integration into SoC-level environments.
• Debug issues during simulation and silicon bring-up.
• Participate in design reviews and cross-functional planning.
• Contribute to design documentation and methodology improvements.

Skills

Performance optimization techniques

Pipelining techniques

Digital design fundamentals

ASIC/SoC development

Education

Bachelor’s/Master’s degree in Electrical Engineering or related field

Tools

Synopsys VCS

Cadence Xcelium

Synopsys Design Compiler

Job description

Bolt Graphics is a semiconductor startup based in Sunnyvale, CA building the fastest and most efficient graphics processors. We pride ourselves on our first principles approach to solving problems. We are energized by our mission to reduce the barrier of entry for content creation and consumption. Our goal is to enable everyone to easily create, simulate and consume immersive experiences as vividly as they can imagine them.

Our Values

• Be Fearless: Unmute yourself. Test boundaries and get proven right.
• Remain Adaptable: Stay comfortable in a continuously changing world. If you’re wrong, concede and move on.
• Educate Your Ego: Selflessly collaborate towards our shared purpose.

About the role

As an RTL Design / Microarchitecture Engineer, you will define and implement key microarchitectural components of our SoC/IP. You will work closely with architecture, verification, and physical design teams to deliver high-performance, scalable, and power-efficient designs.

What you'll do

• Define and develop microarchitecture specifications from high-level architecture requirements.
• Design and implement RTL (SystemVerilog/Verilog) for complex digital blocks.
• Drive performance, power, and area (PPA) optimizations at the RTL and microarchitecture level.
• Collaborate with verification teams to ensure high coverage and design correctness.
• Support integration of IPs into SoC-level environments.
• Work with physical design teams for timing closure, synthesis constraints, and floorplan-aware design.
• Debug and resolve issues during simulation, GLS, and silicon bring-up.
• Participate in design reviews, architecture discussions, and cross-functional planning.
• Contribute to design documentation and methodology improvements.

Required Qualifications

• Bachelor’s/Master’s degree in Electrical Engineering or related field.
• 5–10 years of experience in RTL design and microarchitecture.
• Strong expertise in:
  • Performance optimization and pipelining techniques.
  • Experience with simulation and debugging tools such as:
  • Synopsys VCS/Cadence Xcelium.
  • Familiarity with synthesis and timing concepts (e.g., using Synopsys Design Compiler).
  • Strong understanding of digital design fundamentals (FSMs, pipelines, caches, memory interfaces).
  • Experience working in ASIC/SoC development environments.

Preferred Qualifications

• Experience in one or more domains:
  • CPU, GPU, AI/ML accelerators, networking, or high-speed data processing.
• Knowledge of memory subsystem design (SRAM, cache hierarchies, coherency).
• Familiarity with low-power design techniques (clock gating, power domains).
• Exposure to formal verification or linting tools.
• Experience with GLS, SDF annotation, and silicon debug.
• Understanding of hardware-software interaction (firmware, drivers).

Compensation Range

$160,000–$220,000 per year (California). This range represents the anticipated base pay for this role based in California; the final offer may vary based on qualifications, experience, and location.

Benefits

• Medical, Dental, & Vision - 100% covered premiums.
• Equity - Stock Options.
• 401(k) match.

Bolt is committed to building a diverse and inclusive environment in which we recognize and value each other’s differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. As an equal opportunity employer, all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, genetic information, national origin, age, disability, or status as a protected veteran.