Sr. ASIC Layout Design Engineer

Anysilicon; Goleta (CA); Híbrido; USD 120 000 - 180 000; Tempo integral

Resumo da oferta

Teledyne Technologies Inc. in Goleta, CA seeks a Senior Analog/Mixed-Signal Layout Design Engineer to develop high-performance ROICs for infrared detectors and cameras.

You will collaborate with circuit designers on floor-planning, placement, and routing, ensuring DRC/LVS/PEX compliance and robust parasitic control. The role requires 10+ years in analog/mixed-signal CMOS layout, strong Cadence/Siemens tool experience, and excellent cross‑functional communication.

Qualificações

• Bachelor’s degree in engineering or related field.
• 10+ years of industry experience in analog/mixed-signal layout design for CMOS.

Responsabilidades

• Develop high-quality analog/mixed-signal IC layouts and create GDS databases using Cadence and Siemens software tools.
• Collaborate with circuit designers to optimize floor-planning, placement, and routing.
• Ensure layout integrity and compliance with foundry wafer fabrication through DRC, LVS, PEX, and PDK.
• Interface with ROIC designers, detector engineers, systems engineers, processors, test, and packaging teams to optimize performance and manufacturability.
• Present weekly updates on project schedules and prepare reports for design reviews and customer presentations.
• Handle Export Controlled Information and follow GTC protocol and jurisdictional classification.
• Release and maintain design documents per ISO quality system requirements.

Conhecimentos

Analog/mixed-signal layout design

Calibre verification (DRC, LVS)

Custom cell-based layout

Floor planning / routing

Parasitic minimization techniques

Communication in multidisciplinary 팀

Programming/scripting: SKILL/TCL/Shell

Formação académica

Bachelor's degree in engineering

Ferramentas

Cadence

Siemens software

Calibre

Descrição da oferta de emprego

Teledyne Technologies Inc., Goleta, CA 93117

Job Description

Teledyne Technologies is seeking a Senior Analog/Mixed-Signal Layout Design Engineer to develop high-performance focal-plane array readout integrated circuits (ROICs) for various applications, including infrared detectors and cameras. This role involves collaboration with circuit designers and requires expertise in analog and mixed-signal layout design.

Responsibilities

• Develop high-quality analog/mixed-signal IC layouts and create GDS databases using Cadence and Siemens software tools.
• Collaborate with circuit designers to optimize floor-planning, placement, and routing.
• Ensure layout integrity and compliance with foundry wafer fabrication through DRC, LVS, PEX, and PDK.
• Interface with ROIC designers, detector engineers, systems engineers, processors, test, and packaging teams to optimize performance and manufacturability.
• Present weekly updates on project schedules and prepare reports for design reviews and customer presentations.
• Handle Export Controlled Information and follow GTC protocol and jurisdictional classification.
• Release and maintain design documents per ISO quality system requirements.

Qualifications

• Bachelor’s degree in engineering or related field.
• 10+ years of industry experience in analog/mixed-signal layout design for CMOS circuits.

Skills

• Expertise in analog/mixed-signal layout design, ideally in 180nm, 130nm, or 75nm process nodes.
• Strong understanding of Calibre verification (DRC, LVS) and troubleshooting techniques.
• Experience with custom cell-based layout and top-level floor planning.
• Technical knowledge of wire resistance, coupling capacitance, and minimizing parasitic effects.
• Excellent communication skills and ability to work in a multidisciplinary team.
• Programming/scripting skills in SKILL, TCL, Shell, or Python.