ASIC & FPGA Design Engineer Stf

Anysilicon; Orlando (FL); Hybrid; USD 140,000 - 180,000; Full time

Job summary

Lockheed Martin in Florida is seeking an experienced ASIC & FPGA Design Engineer to own the layout flow from floorplan to tape out. You will collaborate with circuit designers to produce high-performance, parasitic-aware physical designs for advanced defense systems.

The role requires 8+ years in full-custom analog or mixed-signal IC layout, proficiency with 130nm–12nm processes, and experience with Synopsys Custom Compiler and Cadence Virtuoso. A U.S.

Qualifications

• Experience with full-custom analog or mixed-signal IC layout design.
• Ability to perform EMIR analysis and address IR drop and electromigration.
• Familiarity with layout automation and scripting (Python, Tcl, or Perl).

Responsibilities

• Own the entire layout flow from floorplan through tape out.
• Collaborate with circuit designers to create high-performance, parasitic-aware physical designs.
• Create floorplans and optimize area, matching, signal integrity, and power delivery for analog blocks.
• Drive DRC, LVS, and ERC verification for full closure across multiple foundries.
• Perform EMIR analysis to address IR drop and electromigration issues.
• Develop and maintain layout methodology and automation scripts.
• Manage tape out sign-off packages, including documentation and design rule decks.
• Mentor junior layout engineers and foster a knowledge-sharing culture.

Job description

Job Description

Lockheed Martin is seeking an experienced ASIC & FPGA Design Engineer to join their Missiles and Fire Control department. This role involves designing custom analog and mixed-signal ICs for advanced defense systems, with a focus on layout flow from floorplan to tape out.

Responsibilities

• Own the entire layout flow from floorplan through tape out.
• Collaborate with circuit designers to create high-performance, parasitic-aware physical designs.
• Create floorplans and optimize area, matching, signal integrity, and power delivery for analog blocks.
• Drive DRC, LVS, and ERC verification for full closure across multiple foundries.
• Perform EMIR analysis to address IR drop and electromigration issues.
• Develop and maintain layout methodology and automation scripts.
• Manage tape out sign-off packages, including documentation and design rule decks.
• Mentor junior layout engineers and foster a knowledge-sharing culture.

Qualifications

• Associate degree or higher in Electrical Engineering, Electronics Technology, Microelectronics, or a related field.
• 8+ years of experience in full-custom analog or mixed-signal IC layout design.
• Experience with process nodes from 130nm to 12nm, including BCD technologies.
• Proficiency in Synopsys Custom Compiler and Cadence Virtuoso layout environment.
• Experience with physical verification closure (DRC, LVS, ERC, ANT) across multiple foundry processes.
• Ability to obtain a U.S. security clearance.

Skills

• Bachelor's degree in Electrical Engineering or related field (preferred).
• Experience with EMIR analysis and mitigation techniques.
• Scripting or layout automation skills (SKILL, Tcl, Python, or Perl).
• Layout experience with precision analog blocks such as PLLs, ADC/DACs, LDOs, bandgap references, or amplifiers.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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• ASIC Design Services
• Verification
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• Semiconductor IP

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