Senior Analog/Mixed-Signal IC Layout Architect

Anysilicon; Goleta (CA); Hybrid; USD 120,000 - 180,000; Full time

Job summary

Teledyne Technologies Inc. in Goleta, CA seeks a Senior Analog/Mixed-Signal Layout Design Engineer to develop high-performance ROICs for infrared detectors and cameras.

You will collaborate with circuit designers on floor-planning, placement, and routing, ensuring DRC/LVS/PEX compliance and robust parasitic control. The role requires 10+ years in analog/mixed-signal CMOS layout, strong Cadence/Siemens tool experience, and excellent cross‑functional communication.

Qualifications

• Bachelor’s degree in engineering or related field.
• 10+ years of industry experience in analog/mixed-signal layout design for CMOS.

Responsibilities

• Develop high-quality analog/mixed-signal IC layouts and create GDS databases using Cadence and Siemens software tools.
• Collaborate with circuit designers to optimize floor-planning, placement, and routing.
• Ensure layout integrity and compliance with foundry wafer fabrication through DRC, LVS, PEX, and PDK.
• Interface with ROIC designers, detector engineers, systems engineers, processors, test, and packaging teams to optimize performance and manufacturability.
• Present weekly updates on project schedules and prepare reports for design reviews and customer presentations.
• Handle Export Controlled Information and follow GTC protocol and jurisdictional classification.
• Release and maintain design documents per ISO quality system requirements.

Skills

Analog/mixed-signal layout design

Calibre verification (DRC, LVS)

Custom cell-based layout

Floor planning / routing

Parasitic minimization techniques

Communication in multidisciplinary 팀

Programming/scripting: SKILL/TCL/Shell

Education

Bachelor's degree in engineering

Tools

Cadence

Siemens software

Calibre

Job description

Teledyne Technologies Inc. in Goleta, CA seeks a Senior Analog/Mixed-Signal Layout Design Engineer to develop high-performance ROICs for infrared detectors and cameras.

You will collaborate with circuit designers on floor-planning, placement, and routing, ensuring DRC/LVS/PEX compliance and robust parasitic control. The role requires 10+ years in analog/mixed-signal CMOS layout, strong Cadence/Siemens tool experience, and excellent cross‑functional communication.